- Microsoft Corporation (Hillsboro, OR)
- …that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and adoption of ... The Microsoft Silicon Engineering and Solutions Team within SCHIE is...Verification, Validation, DFT, Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. This team supports numerous… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Implementation Engineer ** to join the team. **Responsibilities** You will be ... Microsoft ** Silicon , Cloud Hardware, and Infrastructure Engineering** _(SCHIE)_ is...enablement of quality RTL and collateral file drops to PD , you will be responsible for implementing feedback and… more
- NVIDIA (Santa Clara, CA)
- …see how you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What you'll be doing: + Work ... on SoC IP design, timing closure, power analysis, methodology alignment, and program execution, ensuring success from pre- silicon through post- silicon … more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC- PD Methodology organization is driving the next generation of AI-assisted timing ... closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model… more
- Amazon (San Diego, CA)
- …underserved communities around the world. Come work at Amazon! The Role: As Senior SERDES Design Engineer , you will engage with an experienced cross-disciplinary ... collaborative peer environment. As a member of the Kuiper Silicon Development team, you will be responsible for the...(BIST, loopbacks, etc) - Familiarity with IP deliverables and PD (LEF, LIB, timing closure, EMIR, etc.) - Familiarity… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... clock/data alignment constraints. + Work closely with RTL and PD teams to extract clocking intent and drive accurate...Support timing closure and signoff through timing audits, and silicon correlation. What We Need To See: + Bachelor's… more
- Amazon (Cupertino, CA)
- Description Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create ... of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring… more