- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- NVIDIA (Santa Clara, CA)
- …Electrical or Computer Engineering or equivalent experience. + 8+ years experience in Physical design / Timing . + Experience in full-chip/sub-chip Static ... generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- NVIDIA (Santa Clara, CA)
- …and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design ... What you will be doing: + Working with architects, design leads, physical design leads...Drive the area review process and collaborate with the ASIC design team to identify area, interconnect… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and ... logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …architecture modeling team to determine proper expected design behavior. + Work with physical design engineers to drive timing , area, and power closure. ... We are now looking for a Senior Video ASIC Design Engineer! NVIDIA has been..., and area optimization, static checks, and support of physical design engineers through place and route.… more
- NVIDIA (Santa Clara, CA)
- …. + A deep understanding of ASIC design flow including RTL design , verification, logic synthesis, timing analysis, ECO, and post silicon debug. + Strong ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design...verification engineers. + Deliver a synthesis/ timing clean design while working with the physical … more
- NVIDIA (Santa Clara, CA)
- …is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup ... NVIDIA is looking for an ASIC Design Engineer to join our...Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of...functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design… more
- NVIDIA (Santa Clara, CA)
- …with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding ... We are now looking for a motivated Senior ASIC Design Engineer to join our..., Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with… more
- NVIDIA (Santa Clara, CA)
- By submitting your resume, you're expressing interest in one of our 202 6 Hardware ASIC Design Internships. We'll review resumes on an ongoing basis, and a ... Power and Noise Analysis, Silicon Instrumentation and Measurement + CAD and Physical Design Methodologies (Flow and Tool s Development), Chop Floorplan,… more
- NVIDIA (Santa Clara, CA)
- …EDA, semiconductor, or complex data domains + .Strong background in VLSI/ ASIC design - with deep understanding of timing , constraints, STA, or sign-off ... detection, and timing -exception modeling. + Prior exposure to AI in physical design automation, Silicon/process modeling, or EDA flow automation. +… more
- NVIDIA (Santa Clara, CA)
- …interconnect network and last-level caches , working closely with the physical design team on implementation, synthesis and timing closure as well as working ... between Logic design and Physical design teams responsible for achieving timing , area,... ASIC design flow including RTL design , verification, logic synthesis, prototyping, DFT, timing … more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you ... or Computer Engineering with 6+ years of experience in Physical design .** + **Deep knowledge about industry...chip and block level.** + **Experience with CDC, static timing analysis methodologies and relevant tools.** + **Exposure to… more
- NVIDIA (Santa Clara, CA)
- …products. + Domain & Technical Expertise: Deep knowledge in EDA/VLSI (eg, synthesis, physical design , verification, timing , reliability, or CAD algorithms) ... methods. + Apply deep learning and GPU computing to improve ASIC and VLSI design tool flows. + Collaborate cross-functionally with circuit design ,… more
- Broadcom (San Jose, CA)
- …and package designs for product release sign off + Provide support for timing , physical verification signoff to make IP & ASIC designs robust + Perform WAT & ... extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification + Conducting design reviews &...from manufacturing, technology and packaging **Job Description** + Provide design support for IP & ASIC to… more
- Broadcom (San Jose, CA)
- …improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also ... analysis, diagnostics & yield improvement efforts + Interfacing with the customer, physical design and test engineering/manufacturing teams located globally +… more
- Google (Fremont, CA)
- …scripts, to boost efficiency and coverage. + Forge partnerships with the architecture, physical design , and test engineering teams to guarantee integration and ... qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC /SoC) design , with a focus on both digital logic … more