- Cadence Design Systems, Inc. (San Jose, CA)
- …your responsibilities will span across various aspects for the ASIC frontend flow , which includes RTL integration , maintain the timing constraint, Synthesis, ... Static timing analysis (STA), timing closure, power optimization, and physical verification for both of block and Chip top...ASIC/IP tapeouts. Knowledge of the IP/SoC level timing closure flow and methodology . Strong command of synthesis,… more
- Cisco (San Jose, CA)
- …focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early ... help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical … more
- Paladin Technologies (San Francisco, CA)
- …Company GPM, and operational requirements. + Develop and implement an assertive methodology for follow-up communication and proposal generation of all prospects. + ... Manager Maintains accurate records of job status, changes, material flow and other: + Routinely walks job sites to...+ 6 years of experience within project management, security integration or field experience PREFERRED QUALIFICATIONS: + Minimum of… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …Determine issues/challenges having the most value to the organization and determine methodology to utilize in interpreting and gathering data from multiple sources ... analytics across the organization. Collaborate with IT to ensure data integration , accessibility, performance of BI tools, and the design and implementation… more