- Google (Sunnyvale, CA)
- …or a related field, or equivalent practical experience. + 2 years of experience with System Level Test (SLT) or product engineering. + Experience with ASIC ... benefits. Learn more about benefits at Google. + Develop System Level Test (SLT) solutions for custom... Test (SLT) solutions for custom Application-Specific Integrated Circuits ( ASIC ) and SoC 's by specifying hardware and… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- … ASIC Design Engineers to design and implement the world's leading GPU and SoC 's. With the System - ASIC team, you will contribute to designing multiple ... ASIC designers, and verification engineers to design sophisticated system - level modules such as Floorsweep, In-silicon measurement,...teams in the silicon bring-up process and ensure successful SOC level integration. + You will also… more
- NVIDIA (Santa Clara, CA)
- … ASIC Design Engineers to design and implement the world's leading GPU and SoC 's. With the System - ASIC team, you will contribute to designing multiple ... architects, ASIC designers, and verification engineers to design sophisticated system - level modules such as Floorsweep, In-silicon measurement, Reset and… more
- SpaceX (Redmond, WA)
- …curious engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design, validation, product engineering, ASIC ... RTL in Verilog or SystemVerilog + Experience in designing SoC , DSP, digital communication system datapath blocks,...and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Level I: $122,500.00 - $145,000.00/per… more
- NVIDIA (Santa Clara, CA)
- … System - level modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs ... self-driving cars and the growing field of artificial intelligence. System - ASIC team works closely with System...teams in the silicon bring-up process and ensure successful SOC level integration. + You will also… more
- Meta (Menlo Park, CA)
- …Chip ( SoC ) verification plans, build verification test benches to enable block/IP/sub- system / SoC level verification 2. Develop functional tests based on ... SystemVerilog/UVM methodology or C/C++ based verification 8. 3+ years experience in block/IP/sub- system and/or SoC level verification based on SystemVerilog… more
- Meta (Menlo Park, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....and/or C/C++ based verification 10. 8+ years experience in IP/sub- system and/or SoC level verification… more
- Meta (Menlo Park, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....C/C++ based verification 9. 6+ years of experience in IP/sub- system and/or SoC level verification… more
- SpaceX (Irvine, CA)
- …to solve complex problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with multicore CPU ... curious engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design, validation, product engineering, ASIC … more
- Cisco (San Jose, CA)
- …complex block, cluster or chip- level design + Lead verification for a complete SOC or ASIC i + Prior Experience with Forwarding logic/Parsers/P4 + Formal ... a bachelor's or master's degree + Prior experience with ASIC verification using UVM/ System Verilog. + Prior...Prior experience in verifying complex blocks, clusters and top level for SoC + Prior experience building… more
- Cisco (San Jose, CA)
- Technical Leader ASIC Design - Prototyping Apply (https://jobs.cisco.com/jobs/Login?projectId=1439389) + Location:San Jose, California, US + Area of InterestEngineer ... advanced ASICs that integrate networking, compute, and storage into a single system . With tightly integrated hardware and software solutions, you'll gain exposure to… more
- Qualcomm (San Diego, CA)
- …**Education Requirements** + Bachelor's degree minimum, Master's or PhD preferred. **Keywords:** SoC ( system on chip), Security, ASIC , Digital Design, ... with microcontroller CPUs, Busses (AHB/AXI/others), or Peripherals + Experience with system level architecture, complex subsystems, integration of analog and… more
- Qualcomm (San Diego, CA)
- …open-source hardware projects. + 12+ years of product management experience in custom ASIC or SoC development, including full lifecycle ownership from concept ... RTL, verification, synthesis, physical implementation, and silicon bring-up. + Strong system - level perspective on AI accelerator integration within servers and… more
- Google (Sunnyvale, CA)
- …As a Design Engineer, you will play an important role in designing ASIC / SoC hardware for Artificial Intelligence (AI) and networking accelerators that drive ... . + Work separately and collaboratively to create and review ASIC / SoC subsystem design architecture and microarchitecture specifications. + Develop… more
- Meta (Sunnyvale, CA)
- …netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....for RTL-Synthesis and PrimeTime-STA for the blocks and the top- level including SOC . Analyze the inter-block timing… more
- Qualcomm (San Diego, CA)
- …support both Infra IP level u-architecture optimizations as well as System level application performance verification. The ideal candidate should demonstrate ... of Platform infrastructure HW components such as Memory controllers, System cache, System MMU and Interconnect that...Caches and Memory Technologies (eg LPDDR4/5) + Experience with SoC Performance analysis and debug in pre and/or post-silicon… more
- Meta (Jefferson City, MO)
- …close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable environments for Formal Verification and ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization....with experience in Formal Verification to build IP and System On Chip ( SoC ) for data center… more
- Meta (Sunnyvale, CA)
- …netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...for RTL-Synthesis and PrimeTime-STA for the blocks and the top- level including SOC . Analyze the inter-block timing… more
- Qualcomm (San Diego, CA)
- …+ Work with subsystem and SOC Architects to understand the concepts and high- level system requirements. + Develop detailed Test and Coverage plans based on ... Chip Architects to validate the concepts of core and sub- system level micro-architectures. You will work on...on a Block/Unit of the design. **Qualifications:** Minimum Experience Level should be 2+ years in SOC -… more