• Principal ASIC Design Verification

    Micron Technology, Inc. (Minneapolis, MN)
    …while rapidly growing your abilities. **What's Encouraged Daily** **:** + ASIC design verification with UVM methodologies and Object-Oriented Programming. ... of new UVM and/or Python simulation environments, to develop and execute verification plans in close communication with the design team, and debug complex… more
    Micron Technology, Inc. (02/15/24)
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  • PMTS, Integrated Circuit Digital Design

    Integense (Portland, OR)
    …STA, PnR, DFT and ATPG, extraction, etc. + Experience with pre-silicon RTL design verification , System Verilog or UVM /OVM/VMM, test bench creation, ... designs for best in class ATE products. Responsibilities: + Complete Ownership of the Digital Design and Verification for ATE products - full Front End and Back… more
    Integense (03/27/24)
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  • ASIC Emulation Verification Engineer…

    SpaceX (Irvine, CA)
    …and tools (Veloce, Palladium, Zebu, and/or proFPGA, Protium, HAPS) + Experience with design verification and SystemVerilog, UVM , and C/C++ verification ... computer engineering or computer science + 2+ years of experience with design verification or emulation PREFERRED SKILLS AND EXPERIENCE: + Experience… more
    SpaceX (02/08/24)
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  • Sr. ASIC Verification Engineer

    Micron Technology, Inc. (Minneapolis, MN)
    …written communication skills. **Responsibilities include, but not limited to:** + ASIC/FPGA design verification experience with UVM methodologies and Object ... quality. Typical tasks include development of new simulation environments, execution of verification plans while communicating with design teams, and debugging… more
    Micron Technology, Inc. (03/14/24)
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  • SOC Design Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …in Computer or Electrical Engineering (or equivalent experience). + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... automation, RTL integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and automation… more
    NVIDIA (03/25/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    … automation. + Excellent analytical and problem-solving skills. + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... automation, RTL integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and automation… more
    NVIDIA (03/13/24)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    … automation + Excellent analytical and problem-solving skills + Experience in RTL design (Verilog), verification ( UVM , System Verilog), System-On-Chip ... We are now looking for a CPU Design Methodology Engineer: The complexity of chip development...a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly.… more
    NVIDIA (03/05/24)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology ( UVM ) components to interface between test code and ... cloud servers, clients, and augmented reality. We are looking for a **Senior Design Verification Engineer** to work on leading-edge Intellectual Property (IP)… more
    Microsoft Corporation (03/21/24)
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  • FPGA Design Engineer III

    Textron (Wilmington, MA)
    …and verification skills with Test Bench experience + Experience with OVM/ UVM design verification methodology + Demonstrated software documentation ... used in the future products\. * Conduct prototype testing, integration testing, and design verification and validation testing * Document design , analysis,… more
    Textron (02/09/24)
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  • Senior Application Support Engineer ( UVM

    Siemens Digital Industries Software (Wilsonville, OR)
    …Engineering from an accredited institution + Minimum of 2+ years of Digital Design / Verification experience + Knowledge of VHDL or Verilog, or SystemVerilog RTL ... management skills **Preferred qualifications:** + MS Electronic/Computer Engineering + Knowledge of UVM and System Verilog for Verification + Working knowledge… more
    Siemens Digital Industries Software (03/14/24)
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  • Design Engineering Architect

    Cadence Design Systems, Inc. (Austin, TX)
    …and assertion-based verification methodologies + Exposure to design and verification tools, and methodologies ( UVM or equivalent) + Define and implement ... based on verification test plan + Drive Design Verification to closure based on defined...the industry + 15+ years of hands-on experience in SystemVerilog/ UVM methodology and/or C/C++ based verification +… more
    Cadence Design Systems, Inc. (03/14/24)
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  • National Security Solutions Internship - Trust…

    KBR (Columbus, OH)
    …for assurance analysis + Develop assurance metrics for analysis for a workflow emulated design + Learn basic UVM verification methodology and class libraries ... and presentation skills based on the literature research and results from simulating/emulating/ verification /malware detection in our chip design . As a National… more
    KBR (03/21/24)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    …in verification of design IP with SystemVerilog, advanced methodologies (such as UVM ), and design and verification tools (such as VCS or equivalent ... NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world's leading SoC's and GPU's. This position… more
    NVIDIA (01/26/24)
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  • Design Verification Engineer (US)

    Lightmatter (Mountain View, CA)
    … to develop comprehensive test plans. + Design and implement UVM testbenches for both subsystem-level and full-chip verification . This includes debugging ... Design Verification Engineer Lightmatter is a... Design Verification Engineer Lightmatter is a pioneer in the...role will primarily involve close collaboration with our digital design experts, where you will utilize UVM more
    Lightmatter (02/01/24)
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  • ASIC Engineer, Design Verification

    Meta (Austin, TX)
    …applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure...14. Experience in development of UVM based verification environments from scratch 15. Experience with Design more
    Meta (03/22/24)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design more
    Meta (03/22/24)
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  • FPGA Design Verification Lead

    Teradyne (North Reading, MA)
    …energetic, technically driven Semiconductor Engineer to focus on digital FPGA design verification for products within the Semiconductor Test division. ... verification cycle of Next Generation Automatic Test Equipment (ATE) instrument design verification projects by performing the following duties: + Develop … more
    Teradyne (02/01/24)
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  • FPGA Design Verification Engineer

    Teradyne (North Reading, MA)
    …energetic, technically driven Semiconductor Engineer to focus on digital FPGA design verification for products within the Semiconductor Test division. ... verification cycle of Next Generation Automatic Test Equipment (ATE) instrument design verification projects by performing the following duties: 1. Develop … more
    Teradyne (01/16/24)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …Preferred Qualifications: 14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design verification ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology. 10. 5+ years… more
    Meta (03/22/24)
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  • Silicon Design Verification Engineer

    ManpowerGroup (Philadelphia, PA)
    **Title: Silicon Design Verification Engineer** **Location:** **Philadelphia, PA(Hybrid)** **Duration: 12-months to begin with** Electrical Engineering - ... entire silicon design lifecycle, including system architecture, design verification , RTL digital design ,...SoC. **The Work:** * Testbench development - System Verilog UVM and C tests * Integration/development of C tests/APIs… more
    ManpowerGroup (03/20/24)
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