- ForwardEdge ASIC (a Lockheed Martin Company) (St. Paul, MN)
- …engineering, electrical engineering, or computer science. Relevant prior experience working as an ASIC Design Verification Engineer . Experience with UVM or ... ASIC is seeking skilled and detail-oriented Design Verification Engineers to join our talent network. As a...best practices methodology for functional coverage, assertions, debug, and formal verification . Work closely with digital design… more
- Juniper Networks (Sunnyvale, CA)
- …ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification . Integrate DFT into physical design, ensuring alignment with ... practice, something we call the Juniper Way. As a top-level SOC Physical Design Engineer , you will contribute to all phases of physical design from RTL to the… more
- Capgemini (Seattle, WA)
- Job Description: We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal candidate ... in one or more of the following areas in addition to functional verification : SystemVerilog Assertions (SVA) Formal Verification Emulation Experience with… more
- Huntington Ingalls Industries (Roanoke, VA)
- …Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies is seeking out-of-the-box thinkers ... corner-case bugs and vulnerabilities in the gate-level netlists of FPGA and ASIC designs. Candidates for this position will help lead teams of digital… more
- Cisco Systems Inc (Maynard, MA)
- …long-haul and ultra-long haul telecommunication networks. This role sits on our ASIC team providing infrastructure support for RTL implementation to gates. Your ... Impact You will collaborate with Acacia's ASIC and Hardware teams in the engineering organization to...partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal… more
- Meta (Jefferson City, MO)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Lockheed Martin (Denver, CO)
- **Description:** Join Our Team as an ** ASIC & FPGA Lead Verification Engineer ** where you will support over 50 different programs and research and ... world, and are seeking a highly talented and motivated ** ASIC & FPGA Verification Engineer **...test pattern generation, logic equivalency checking, linting and/or other formal design checks\. * Knowledge of space\-grade/qualified FPGAs and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 17.… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Cisco (San Jose, CA)
- ASIC Verification Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431425) + Location:San Jose, California, US + Area of InterestEngineer - ... Verilog / UVM programming + 4+ Years post graduate ASIC Verification processes, methodologies, flows and tools...Understanding of Networking technologies and concepts + Experience with Formal verification + Experience with Post-silicon lab… more
- Cisco (San Jose, CA)
- ASIC Design Verification Engineer Apply...MMU. + Experience with Veloce/HAPS is a plus + Formal verification (iev/vc formal ) knowledge is ... Work With:** You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with … more
- SpaceX (Sunnyvale, CA)
- Principal ASIC Verification Engineer Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. PRINCIPAL ASIC VERIFICATION ENGINEER (SILICON ENGINEERING)...+ Strong debugging skillset + Experience in constrained random verification + Experience with Formal verification… more
- Qualcomm (San Diego, CA)
- …that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate ... smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design,...Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Amazon (North Reading, MA)
- …in the validation of FPGAs using test benches, which can be reused for the ASIC implementation - Run formal verification of complex blocks to ensure ... preferably in communication systems - Familiarity with Matlab - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an… more
- Amazon (Sunnyvale, CA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- Amazon (San Diego, CA)
- …run regressions, collect coverage matrices and report progress to the program * Run formal verification of complex blocks to ensure functional correctness * Work ... (DSP or MODEM) implementations * Familiarity with Matlab * Familiarity with formal verification techniques * Strong written and verbal skills Amazon is an equal… more
