- Juniper Networks (Sunnyvale, CA)
- …practice, something we call the Juniper Way. As a top-level SOC Physical Design Engineer , you will contribute to all phases of physical design from RTL to the ... among blocks and sub-chips at the chip level, generating block/chip-level static timing constraints. Arrange, analyze, and optimize feedthrough and repeaters among… more
- Marvell Technology, Inc. (Santa Clara, CA)
- …in a collaborative and innovative environment. We are seeking a Senior Staff Physical Design Engineer - Static Timing Analysis (STA) to join our growing team. In ... on-time and high-quality tape-outs. What You Can Expect Perform full-chip and block-level static timing analysis for advanced ASIC designs Develop, maintain, and… more
- DBSI Services, Inc. (Milpitas, CA)
- Benefits: 401(k) 401(k) matching Relocation bonus Job Title: Physical Design Engineer Location: Milpitas, CA Primary Responsibilities: Pre-layout STA to ascertain ... Optimization, Clock TreeSynthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis andPhysical Verification) Presentations… more
- Cisco Systems Inc (Maynard, MA)
- …long-haul and ultra-long haul telecommunication networks. This role sits on our ASIC team providing infrastructure support for RTL implementation to gates. ... Your Impact You will collaborate with Acacia's ASIC and Hardware teams in the engineering organization to...closely with RTL designers to debug and root-cause physical implementation issues related to design, tools, etc. and arrive… more
- Meta (Sunnyvale, CA)
- … Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform ... technical field, or equivalent practical experience 9. 6+ years of experience in static verification tools 10. Experience with Lint, Clock Domain & Reset Domain… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...analysis , SI noise analysis 11. Experience with running Static Timing Analysis for full chip using DMSA 12.… more
- The Boeing Company (Huntington Beach, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... Experience with ASIC /FPGA design or verification + Experience with ASIC /FPGA architectural definition, and detailed design implementation and functional… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- SpaceX (Bastrop, TX)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... area targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking,...path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation . What we need to see: + Hold a BS in Electrical or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
- NVIDIA (Santa Clara, CA)
- …generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
- Amazon (Austin, TX)
- …high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA tools and flows ... of the design automation and methodology team and deliver digital design implementation flows to design teams using various silicon processes - Develop, regress,… more
- Google (Sunnyvale, CA)
- …AI/ML-driven systems. In this role, you will work on the physical implementation of Application-specific Integrated Circuits ( ASIC ) using advanced technology ... equivalent practical experience. + 5 years of experience in static timing analysis. + Experience in full chip timing...creation for timing convergence, and final timing sign-off for ASIC tape outs. + Utilize Perl, Python, TCL, or… more
- L3Harris (Camden, NJ)
- …sea and cyber domains in the interest of national security. Job Title: Sr ASIC /FPGA VHDL Design Engineer Job Code: 24260 Job Location: Camden, NJ-relocation ... with every other Friday off Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff (SMES) will be part of the… more
- Broadcom (San Jose, CA)
- …working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with the ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...physical implementation team from initial floor planning to final timing… more
- Cisco (Maynard, MA)
- …long-haul and ultra-long haul telecommunication networks. This role sits on our ASIC team providing infrastructure support for RTL implementation to gates. ... Physical Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444081) + Location:Maynard, Massachusetts, US +...**Your Impact** You will collaborate with Acacia's ASIC and Hardware teams in the engineering organization to… more
