- Qualcomm (San Diego, CA)
- …in 5nm, 4nm and beyond (process technologies). You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and ... Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR… more
- Hewlett Packard Enterprise Development LP (Sunnyvale, CA)
- …technology company in Sunnyvale, California, seeks an experienced engineer to join the Physical design team. The role involves optimizing floorplan and timing ... closure while validating designs with the Verification team. Candidates must have a Bachelor's degree in Electrical Engineering and over 10 years of experience, alongside strong analytical skills and proficiency in Verilog/System Verilog. This position… more
- Chelsea Search Group (Minneapolis, MN)
- Lead ASIC Design Engineer Minneapolis, MN (onsite/hybrid). US Citizen or US Permanent Resident. Full-Time + Health Benefits + 401K Plan with profit sharing + PTO ... + Stock Option Plan. Job Description As ASIC Design Lead, you will play a... constraints for the entire chip. Work closely with physical design teams to ensure successful place-and-route.… more
- SPACE EXPLORATION TECHNOLOGIES CORP (Sunnyvale, CA)
- …this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in ... timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality...and weekends as needed COMPENSATION & BENEFITS Pay range: ASIC Design Engineer/Senior: $170,000.00 - $230,000.00 per… more
- Google Inc. (Sunnyvale, CA)
- …a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, ... or equivalent practical experience. 7 years of experience with physical design (eg from RTL to GDSII,...Experience working with external partners on Physical Design (PD) closure. Experience in Static Timing … more
- Avicena Inc. (Sunnyvale, CA)
- …details, and verification results. Collaboration: Interface with architecture, verification, physical design (backend), and silicon validation teams to ... define test plans, review coverage, and debug functional and timing issues using simulation tools. Synthesis and Timing...ASIC Flow Knowledge: Solid understanding of the complete ASIC design flow from specification to tape‑out.… more
- Eridu Corporation (San Francisco, CA)
- …including throughput, latency, power and area efficiencies. Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design ... Software Control Plane interface architecture is highly desirable. Understanding of physical design implications on packet processing and buffering architecture… more
- NVIDIA Corporation (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL.* Collaborate with Physical design and timing team to evaluate Clocking concerns and ... Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.* Engage with multiple teams and … more
- Cornelis Networks, Inc. (San Jose, CA)
- … coverage. Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure. Support post-silicon validation, ... design for Ethernet protocols relevant to adapters and switches. Familiarity with timing closure and modern physical design methodologies. Proven ability… more
- Apple Inc. (Santa Clara, CA)
- …Work on front-end netlist and area/ timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem. ... Minimum Qualifications 10 + years of full time ASIC design experience in: Memory system development PPA (performance/power/area) analysis Cache design … more
- Hewlett Packard Enterprise Development LP (San Jose, CA)
- …reliability of our high-speed, high-complexity ASICs. You will work closely with front-end design , physical design , and verification teams to architect and ... ASICs at 3nm and beyond.* Collaborate with RTL and physical design teams to integrate scan, compression,...& Experience: 10+ years of hands-on DFT experience in ASIC design , preferably in networking or high-speed… more
- Broadcom Inc. (San Jose, CA)
- …C++.* Demonstrate the ability to work through technology challenges and physical implementation issues associated with high-performance design implementations.* ... of Matlab, Perl, Python or other scripting languages.* Familiarity with digital chip design concepts, such as clocking, timing , pipelines, and performance vs… more
- Apple Inc. (Sunnyvale, CA)
- …includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own STA ... 3+ years of relevant industry experience. Hands-on experience in ASIC timing constraints generation and timing...collaborate with a lot of different groups (eg digital design , DFT, physical design , etc.).… more
- Apple Inc. (San Diego, CA)
- …includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own STA ... 10+ years of relevant industry experience. Hands‑on experience in ASIC timing constraints generation and timing...collaborate with a lot of diverse groups (eg digital design , DFT, physical design , etc.).… more
- Nutanix (San Diego, CA)
- A leading technology firm is seeking a Physical Design Engineer to join their team in San Diego, CA. The ideal candidate will have extensive experience in ... ASIC design , focusing on clock tree synthesis and verification. This role requires strong scripting skills and the ability to collaborate across functional teams… more
- Qualcomm (San Diego, CA)
- …future for all. QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. ... design , verify, and deliver complex Physical Design solutions from netlist and timing constraints...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- Arm Limited (San Diego, CA)
- …relevant technical fields. 7+ years of proven experience in ASIC Implementation, Synthesis, Timing constraints, UPF, Physical design , STA and Timing ... design team to develop design intent, timing constraints required to enable implementation. Synthesis, Physical... timing constraints required to enable implementation. Synthesis, Physical design and implementation of CPU and… more
- Theconstructsim (Milpitas, CA)
- …BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design ; Experience in an SoC product development ... top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock… more
- Broadcom Inc. (San Jose, CA)
- …concept to product release, becoming a key contributor to all aspects of physical ASIC design .**Job Duties and Responsibilities may include: Communicating ... R&D Engineer Physical Design page is loaded## R&D...major segment of the semiconductor industry-including AI-to build advanced ASIC solutions.Join the Design Implementation team within… more
- Central Business Solutions, Inc (San Jose, CA)
- …logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology ... Title: Physical Design Engineer Location: 100% Remote...design of an end-to-end IP or integration of ASIC /SoC design Minimum Qualifications: Bachelor's degree in… more
