- MatX (Mountain View, CA)
- …leading-edge process nodes. Responsibilities include: Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and ... synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing , power estimation, EMIR, physical verification) Plan and drive intermediate… more
- DBSI Services, Inc. (Milpitas, CA)
- Benefits: 401(k) 401(k) matching Relocation bonus Job Title: Physical Design Engineer Location: Milpitas, CA Primary Responsibilities: Pre-layout STA to ascertain ... feasibility, timing constraint validation and feedback tocustomers and design teams...of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product developmentorganization… more
- SiMa Technologies (San Jose, CA)
- …learning being a key component. Areas of Focus : Design methodology , micro-architecture, RTL. Static timing analysis, verification/emulation support, back-end ... Description Job Title: Sr Principal Engineer , Hardware Design Job Location: San Jose, CA...will include RTL coding, design and reviews, synthesis, static timing analysis, and coverage analysis. This means working very… more
- Tenstorrent (Austin, TX)
- …are growing our team and looking for contributors of all seniorities. CTS Methodology Lead for high-performance designs going into industry leading CPU and AI/ML ... architecture. This role involves owning and driving CTS methodology development and implementation, and help define and refine clock architecture strategies (eg,… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready… more
- Meta (Austin, TX)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Timing , Area, Power 5. Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA) 6.… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... with multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. + Contribute to full chip integration and timing methodology /analysis. + Develop and analyze functional coverage. + Help ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) +...define, evolve, and support our design methodology . + Collaborate with the verification team to address… more
- Meta (Austin, TX)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power 2. Debug the timing /area/congestion… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...optimization tasks + Collaboration with physical design to address timing , area, congestion tradeoffs + Drive timing … more
- Meta (Sunnyvale, CA)
- … Implementation Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... Level Netlist for Timing , Area, Power 6. Developing Automation scripts and Methodology for all Front-end tools including (Lint, CDC, RDC,) 7. Work closely with… more
- Cisco (San Jose, CA)
- ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441220) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... product teams, working together to ensure the successful deployment of the ASIC in products. **Your Impact** + Development of high-performance designs/ASICs from… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...NOC, Memory and Peripheral Subsystems 13. Experience with Synthesis, Timing Closure and Formal Verification Methodology 14.… more
