• Sr. Full Chip Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
    SpaceX (11/14/25)
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  • Design Engineer - Chip Floorplanner

    Broadcom (Fort Collins, CO)
    …exceeding 1 GHz, from concept through production. **Role Overview** This Floorplanning Engineer role focuses on chip -level physical architecture and integration ... for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional… more
    Broadcom (11/12/25)
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  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The day-to-day ... 1). Defining in the microarchitecture and implementing design of chip top level modules for L2/L3 Network Switching and...ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks,… more
    Broadcom (11/19/25)
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  • Silicon Photonics Chip Assembly & Packaging…

    Global Foundries (Malta, NY)
    …information, visit www.gf.com . Summary of Role: This hands-on Package and chip assembly Engineering role will develop industry leading advanced packaging utilizing ... required - Wafer level processing for TSV's, RDL, and bumping, advanced flip chip on chip and chip on wafer assembly, Wafer singulation, and chip more
    Global Foundries (10/23/25)
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  • Chip Power Integrity Engineer

    Broadcom (Fort Collins, CO)
    …**Job Description:** **You will fit this role if:** + You are an expert in full- chip power integrity analysis using state of the art tools that are able to parallel ... level through PDN simulations **More specifically we are looking for a chip power integrity expert with the following hands-on know-how:** + Developed innovative… more
    Broadcom (11/06/25)
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  • Senior Design Engineer

    Global Foundries (Richardson, TX)
    …markets. For more information, visit www.gf.com. Summary of Role: A Senior System-on- Chip Design engineer to design Automotive Microcontrollers. The candidate ... specifications based on requirements. + Hands on development of submodule and chip level RTL. + Contribute to the development of frontend design flows… more
    Global Foundries (11/07/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and ... the world's most advanced AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness of this critical technology.… more
    NVIDIA (11/13/25)
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  • Silicon Validation Engineer , Reality Labs

    Meta (Sunnyvale, CA)
    …teams (ie, architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip , and product engineer teams) to generate validation reports ... content. The Reality Labs team seeks a Silicon Validation Engineer .As a Silicon Validation Engineer , you will..., Reality Labs Responsibilities: 1. Responsible for System on Chip and end-to-end system validation plan development, execution and… more
    Meta (10/22/25)
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  • Chip Architect

    Texas Instruments (Dallas, TX)
    We are seeking a talented ** Chip Architect** to join our ACS team which develops cutting edge ASSP ICs. This individual will play a key role in **architecting ... design, layout, verification, and test/validation teams to define the chip architecture to meet all project requirements. + Own...ensure smooth integration according to plan. **Why TI?** + Engineer your future. We empower our employees to truly… more
    Texas Instruments (11/07/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased over the years. We are now packing tens of ... billions of transistors in a chip to meet the growing computing demand in a...NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL… more
    NVIDIA (11/20/25)
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  • Package Design Engineer

    Broadcom (Fort Collins, CO)
    …apply.** **Job Description:** Broadcom is seeking an experienced IC package-design engineer for complex flip- chip -BGA packages for industry-leading ASICs with ... prioritize, & track your work across 2+ projects simultaneously + General flip- chip BGA package design & engineering + Project management and customer interface… more
    Broadcom (12/03/25)
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  • Principal/Senior Principal Electromechanical…

    Northrop Grumman (Baltimore, MD)
    …Grumman Mission Systems is seeking a Principal/Senior Principal Electromechanical Design Engineer to join our team of qualified, diverse individuals. This position ... and production support of state-of-the-art RF, digital, and mixed signal multi- chip modules (MCMs), Printed Wiring Boards (PWBs), and Circuit Card Assemblies… more
    Northrop Grumman (09/24/25)
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  • Electronics Package Design Engineer

    MetaOption, LLC (Ronkonkoma, NY)
    Electronics Package Design Engineer Primary Skills - package layout, signal integrity, flip chip , bga, ceramic, multi- chip modules, electronics packaging, ... system in package, cadence Job Description Electronics Packaging Design Engineer We are seeking an experienced Electronics Packaging Design Engineer to join our… more
    MetaOption, LLC (10/25/25)
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  • Principal/ Senior Principal Digital ASIC Circuit…

    Northrop Grumman (Jessup, MD)
    …new advantages to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital circuits. Must be proficient in ... below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + Bachelor's degree in a technical area...+ Current security clearance or eligibility + Experience with chip level integration and ASIC chip lead… more
    Northrop Grumman (12/05/25)
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  • Senior System Software Engineer , EDA…

    NVIDIA (Santa Clara, CA)
    …systems that provide real-time understandings of our sophisticated, distributed infrastructure. As an engineer on our team, you will play a key role in building the ... What you'll be doing: + Collaborate closely with internal chip design teams to understand their workflows and determine...needs to help improve the overall efficiency of our chip development process. + Compose, build and maintain robust… more
    NVIDIA (12/05/25)
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  • Senior DFT Static Timing Analysis Engineer

    Google (Sunnyvale, CA)
    Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... practical experience. + 5 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static… more
    Google (12/05/25)
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  • Post-Silicon Systems Validation Engineer

    Amazon (Cupertino, CA)
    …boards and servers at scale. Key job responsibilities As a Senior Validation engineer , you are responsible for validating the chip and system architecture ... stack of Silicon, PCB, High Speed components eg, HBM, PCIe and Chip to Chip , inter-systems and system to system. Diving deep into new technology hardware… more
    Amazon (11/13/25)
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  • ATE Test Development Engineer

    Broadcom (Fort Collins, CO)
    …ASIC Products Division is seeking a candidate for an ATE Test Development Engineer . This position is at our Fort Collins Development Center in Colorado. The ... and functional tests domains. * Qualification Support : Assist with chip testing to support qualification related testing. Examples including failure verification… more
    Broadcom (10/30/25)
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  • Senior ASIC Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to challenge ... GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such...+ Background with logic synthesis at either block or full- chip level, at project execution and/or flow development. +… more
    NVIDIA (10/22/25)
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  • EDA Workflow Optimization Engineer

    NVIDIA (Santa Clara, CA)
    …GPU in 1999 to reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering ... teams worldwide. You will understand workflows covering the full chip design process from inception through study, architecture, design, verification, emulation,… more
    NVIDIA (10/03/25)
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