- Qualcomm (San Diego, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (San Diego, CA)
- …teams (RTL, Physical Design , Circuits, CAD) to address critical physical design challenges in CPU implementations. + Develop innovative techniques ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU ...PPA Pathfinding Engineer, you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams… more
- Qualcomm (Austin, TX)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and...nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical … more
- NVIDIA (Hillsboro, OR)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is seeking...fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks.… more
- Qualcomm (San Diego, CA)
- … operations for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + ... Engineer, you will lead innovative Central Processing Unit ( CPU ) design efforts that have a critical...Should have good exposure to high frequency design convergence for physical design … more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer, you will work with ... + Experience with Synthesis, place and route and signoff timing /power analysis. + Knowledge of high performance and low... design , Circuits, CAD) to solve key physical design problems in CPU … more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** We are hiring a talented...simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power… more
- Qualcomm (Santa Clara, CA)
- …synthesis, place & route and tape out flows. Roles and Responsibilities + Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP ... and physical design teams to design , floorplan and integrate the CPU designs...+ Proficiency in synthesis, place and route, and signoff timing /power analysis. + Expertise in block-level implementation as well… more
- Qualcomm (Austin, TX)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …skills and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out ... CPU , GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...(or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in… more
- Amazon (Sunnyvale, CA)
- …device physics, custom/semi-custom implementation techniques - Experience solving physical design challenges across various technologies such as CPU , DDR, ... generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate...pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification,… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... design the GPU or CPU clocks to satisfy all the architectural/ design / physical constraints. + Improve Power, Performance, and Area (PPA) of innovative… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Microsoft Corporation (Austin, TX)
- …to develop test plans and ensure functional correctness + Interface with performance modeling, physical design , design for test, and other teams to optimize ... design flow including microarchitecture, RTL coding, Lint, CDC, timing closure, etc + Collaborate with team members to...linting, etc). + Demonstrated proficiency in Computer Architecture, Digital Design , CPU /SoC design principles as… more
- Microsoft Corporation (Austin, TX)
- …the verification team to ensure functional correctness + Interfacing with performance modeling, physical design , design -for-test, and other teams to deliver ... various functional block RTLs into SoC RTL + Performing design quality checks such as timing closure,...engineering experience OR equivalent experience. + 1+ years logic design experience as a part of either CPU… more
- Amazon (Sunnyvale, CA)
- …robotics. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance ... and trade-offs - Experience in closing full-chip and subsystem timing working with synthesis and static timing ...RTL generation or automation - Experience working closely with physical design teams to develop highly optimized… more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... FPGA design flow (eg synthesis, timing closure, formality...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- Broadcom (San Jose, CA)
- …knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough knowledge of high-speed Ethernet networking and ... and working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with… more
- Microsoft Corporation (Mountain View, CA)
- …program you will be interacting with various teams, including architecture, verification, and physical design , ensuring that the design is implemented and ... Fabric/Network On Chip or Networking ASICs or Complex Control Logic + Experience with CPU or graphics core design . + Experience with Complex algorithmic designs… more
- Microsoft Corporation (Santa Clara, CA)
- …deliver significantly superior performance compared to CPU -based alternatives We're seeking a Physical Design Engineer. As part of our DPU silicon team in ... Santa Clara, you'll take on all aspects of Physical Design from RTL to GDS signoff....of important designs and drive them tapeout, meeting all timing , physical , electrical, and manufacturing requirements: +… more