- US Tech Solutions (Goleta, CA)
- …independently and take ownership of verification deliverables within a UVM /SystemVerilog environment. + The engineer will collaborate with design, ... **Job Description:** + The Verification Engineer will contribute to the... prior to tape-out. **Responsibilities:** + Perform pre-silicon functional verification of digital designs using UVM and… more
- Actalent (Wayne, NJ)
- **NEW FPGA DESIGN VERIFICATION ENGINEERING OPPORTUNITY SUPPORTING A NEXT-GEN RADAR SYSTEM FOR A TOP AEROSPACE & DEFENSE COMPANY IN THE WORLD ** Job Description ... The role involves the design verification of VHDL developed for an FPGA ,...coverage closure. The code will be developed using SystemVerilog/Universal Verification Methodology (SV/ UVM ) following established styles and… more
- BAE Systems (Westminster, CO)
- …incentives may be available based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR** ... used across multiple projects. + Work in a System Verilog/ UVM environment developing tests, testbenches, UVM components,...regressions/testlists. + Be responsible for generating and executing the FPGA Verification Test Plan and FPGA… more
- Lockheed Martin (North Andover, MA)
- **Description:** Join Our Team as a **ASIC/ FPGA Verification Engineer ** where you will work on the development of a sophisticated state\-of\-the\-art ... Space's Silicon Solutions team and seeking a future\-looking Principal Verification Engineer who is able to case...of FPGA and ASIC devices utilizing modern verification methodologies such as UVM \. * Experience… more
- Northrop Grumman (Jessup, MD)
- …+ Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl, Python, ... for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a... FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting… more
- BAE Systems (Westminster, CO)
- …development environment to provide continuously evolving capabilities in space payloads. As an FPGA Verification engineer , you will work with a team ... including Xilinx Vivado/Vitis and Mentor Modelsim/Questasim. + Experience with OVM/ UVM Verification methodologies. + Ability to work...based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K… more
- BAE Systems (Nashua, NH)
- …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117194BR** EEO ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa… more
- BAE Systems (Cedar Rapids, IA)
- …may be available based on position level and/or job specifics. **Senior Principal Engineer - ASIC/ FPGA Verification (Hybrid)** **117726BR** EEO Career Site ... navigation missions. BAE is looking for experienced senior level ASIC/ FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with ASIC/ FPGA design and verification tools (Siemens or… more
- Teradyne (North Reading, MA)
- …Overview Our Logic Design Engineering team is seeking a digital logic Verification Engineer who preferably also has experience in FPGA design. + The primary ... focus of the role will be FPGA verification including: + Review of design...logic verification , preferably using SystemVerilog & Universal Verification Methodology ( UVM ) + Familiarity with PCIe,… more
- Lockheed Martin (Orlando, FL)
- …Design Engineer to join our team\. As an ideal candidate, you're an experienced FPGA engineer with a strong background in FPGA design, development, and ... **Description:** You will be the FPGA Design Engineer for our team,...with debugging and troubleshooting complex digital systems \-Knowledge of UVM and experience with UVM \-based verification… more
- Lockheed Martin (Orlando, FL)
- **Description:** You will be a FPGA Design & Verification Engineer at Lockheed Martin, responsible for designing, simulating, and integrating ... cutting\-edge technologies\. **What You Will Be Doing** As a FPGA Design & Verification Engineer ,...* Utilizing prior experience with Microchip FPGAs, Xilinx FPGAs, UVM , and GitLab to support FPGA design… more
- Lockheed Martin (Orlando, FL)
- **Description:** You will be the ASIC & FPGA Design Engineer at Lockheed Martin, responsible for designing, simulating, and integrating Field\-Programmable ... **What You Will Be Doing** As the ASIC & FPGA Design Engineer , you will perform requirements...* Utilizing prior experience with Microchip FPGAs, Xilinx FPGAs, UVM , and GitLab to support FPGA design… more
- L3Harris (Rochester, NY)
- …candidates must have experience with RTL development using VHDL, as well as FPGA verification methodologies using SystemVerilog. Candidate will be required to ... the interest of national security. Job Title: Lead, Electrical Engineer - FPGA Job Code: 30336 Job Location: Rochester,...analyze requirements, create FPGA specifications/development plans, create FPGA verification… more
- Honeywell (Plymouth, MN)
- …power, and area trade-offs. + Develop and implement verification plans for FPGA designs. + Utilize UVM methodology to create component and top-level test ... and service solutions, is seeking an experienced and passionate FPGA Design Engineer to join our dynamic...of professional experience in FPGA design and/or verification . + Proficiency in UVM methodology and… more
- RTX Corporation (Tucson, AZ)
- …the world, from the ground to exoatmospheric environments and into space. As a **Senior FPGA Design Engineer ** you will develop FPGA designs for all major ... FPGA /ASIC design (VHDL and/or Verilog coding) or FPGA /ASIC verification (SystemVerilog coding) + Xilinx or...serial interfaces and multi-gigabit transceivers (MGTs) + Constrained random verification in UVM using System Verilog +… more
- L3Harris (Herndon, VA)
- …and cyber domains in the interest of national security. Job Title: Sr. Specialist ASIC/ FPGA Senior Design Engineer Job Code: 30428 Job Location: Herndon, VA ... 100 countries. Job Description: Reporting to the Manager, Engineering (ASIC/ FPGA ), the Senior Design Engineer will be...Vivado HLS, AND/OR Mentor Calypto). + Experience with Universal Verification Mythology ( UVM ). + Experience with project… more
- UIC Government Services and the Bowhead Family of Companies (Dahlgren, VA)
- **Overview** Bowhead is seeking a FPGA Engineer to join our team that supports the Hypersonics Projectiles Division of the Naval Surface Warfare Center Dahlgren ... systems engineering teams to develop integrated solutions. * Develop and maintain FPGA testbenches for functional verification . * Contribute to system… more
- RTX Corporation (Cedar Rapids, IA)
- …analysis, linting analysis, LEC, and clock-domain-crossing analysis. + Perform ASIC/ FPGA /SoPC verification using inspection, analysis, simulation, and test ... you interested in becoming part of a growing Avionics FPGA /ASIC team? This position is for a highly experienced,...for a highly experienced, highly motivated Electrical or Computer Engineer that will be involved in the design, implementation,… more
- Micron Technology, Inc. (Boise, ID)
- …communicate and advance faster than ever. **Job Description** As an Electrical Design Engineer - ( FPGA /ASIC) in the Systems Integration Group (SIG) at Micron ... like Siemens ModelSim/QuestaSim, AMD/Xilinx Vivado, or Altera/Intel Questa + Knowledge of UVM methodology for verification . + Expertise in laboratory debug… more
- L3Harris (Cincinnati, OH)
- …and QuestaSim is our simulation tool. The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and C# based ... / FPGA designs will include various sensor interfaces, sequence verification , A/D and D/A interfaces, communication protocols, state machines, timer chains, etc.… more