• Senior Rtl /FPGA Design Egineer

    Medtronic (Lafayette, CO)
    …of the programmable logic elements of medical capital equipment used in surgery. Hardware interfaces such as DAC, ADC, LCD display, DSP algorithms implemented in PL ... following and other duties may be assigned. Design FPGA RTL systems and close timing for advanced medical equipment...multiple products and platforms Debug prototype FPGA designs in hardware and in simulation Collect and refine FPGA and… more
    Medtronic (06/20/25)
    - Save Job - Related Jobs - Block Source
  • Senior Member Engineering Staff-ASIC/FPGA…

    L3Harris (Camden, NJ)
    …with us, shaping the future of defense technology! Job Description: Reporting to the Manager , Engineering (ASIC/FPGA), the Senior Member of Engineering Staff ... national security. Job Title: ASIC/FPGA Design: Senior Member of Engineering Staff (SMES) Job Code: 26283 Job Location: Camden,...system requirements and developing detailed architecture + Execute design ( RTL AND/OR HLS (C++ to RTL )) and… more
    L3Harris (07/23/25)
    - Save Job - Related Jobs - Block Source
  • Principal Design Engineer Manager - AI…

    Microsoft Corporation (Austin, TX)
    Microsoft Silicon, Cloud Hardware , and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for ... to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high...paramount importance. To achieve this goal, the AI Silicon Engineering (AISiE) team is instrumental in defining and delivering… more
    Microsoft Corporation (07/18/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    ASIC Engineering Technical Leader - SDC Apply (https://jobs.cisco.com/jobs/Login?projectId=1434557) + Location:San Jose, California, US + Area of InterestEngineer - ... Hardware + Compensation Range168800 USD - 241200 USD +...block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. + Create fullchip… more
    Cisco (07/05/25)
    - Save Job - Related Jobs - Block Source
  • CPU Cache Subsystem Design Manager

    Google (Portland, OR)
    Minimum qualifications: + Bachelor's degree in Electrical Engineering , Computer Engineering , Computer Science, or a related field, or equivalent practical ... of experience in high-performance CPU, cache subsystem or AI accelerator logic/ RTL design including microarchitecture definition and PPA optimizations. + 6 years… more
    Google (07/02/25)
    - Save Job - Related Jobs - Block Source
  • ASIC SoC Manager , Amazon Camera ASIC Team

    Amazon (Sunnyvale, CA)
    Description As an SoC Manager , you will lead a team responsible for executing and delivering complex IPs and silicon that ship in the Blink and Ring camera products. ... Key job responsibilities - Lead, hire and develop a world-class engineering team for silicon development, including expertise in front-end microarchitecture, … more
    Amazon (07/10/25)
    - Save Job - Related Jobs - Block Source
  • Technical Program Manager , ASIC

    Amazon (San Diego, CA)
    …connectivity. The Project Kuiper team is looking for a Technical Program Manager with experience in ASIC/SOC development, from architecture to pre-production stages, ... and program management. The role will interface with cross-functional engineering and program/product management teams to develop ASIC/SOCs solutions that… more
    Amazon (06/10/25)
    - Save Job - Related Jobs - Block Source
  • FPGA Design Manager

    BAE Systems (Manchester, NH)
    …split between working onsite and remotely. BAE Systems is seeking an FPGA Design Manager to work within our Electronic Systems business area leading an FPGA Design ... aptitude and leadership skills. Experience leading design engineers within multi-disciplined engineering teams through all phases of an ASIC or FPGA development… more
    BAE Systems (06/19/25)
    - Save Job - Related Jobs - Block Source
  • Senior Manager of Digital IC-Design

    Renesas (San Jose, CA)
    Senior Manager of Digital IC-Design Job Description This is a **Senior Manager ** position for a qualified individual to work in Renesas' Analog and Connectivity ... for future products. Qualifications + MSEE or PH.D. in Electrical Engineering . + **8+ years of semiconductor industry experience.** + Experience managing… more
    Renesas (07/18/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Design Engineer - Design & Timing Constraints

    Cisco (San Jose, CA)
    …+ Location:San Jose, California, US + Area of InterestEngineer - Hardware + Compensation Range152400 USD - 221800 USD + Job TypeProfessional ... and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all...timing modes + Option to also do block level RTL design or block or top-level IP integration +… more
    Cisco (06/25/25)
    - Save Job - Related Jobs - Block Source
  • Technical Sourcer

    Silvus Technologies (Los Angeles, CA)
    …passive candidates and stakeholders. + Understanding of technical roles (eg, software development, hardware engineering , digital design, etc.). + **Must be a US ... Hunter, etc.). + Demonstrated knowledge of technical job profiles, eg Software Development, Hardware Engineering , R&D, Product Design, Sales Engineering . +… more
    Silvus Technologies (07/12/25)
    - Save Job - Related Jobs - Block Source