- Apple Inc. (San Francisco, CA)
- …to develop new substrate technologies from concept to HVM for Apple packaging roadmap. Work with cross‑functional groups to define & optimize new package ... San Francisco Bay Area, California, United States Hardware Our Hardware Technology Packaging team invents, designs, develops, and integrates electronic packaging … more
- Eridu Corporation (San Francisco, CA)
- …augmented reality contact lens). Position Overview We are seeking an Advanced Packaging Engineer to lead the development, integration, and production enablement ... of next-generation multi-die packaging solutions, including 2.5D CoWoS, bridge-based, and high-density chiplet assemblies. This role drives end-to-end packaging … more
- Apple Inc. (Santa Clara, CA)
- …no telling what you could accomplish! We are looking for versatile and passionate IC Packaging Engineer to join our team! Description You will be responsible for ... IC packaging development Work with cross-functional teams and lead SoC...cause investigations across multiple domains (wafer level processes, assembly, substrate ), process excursions, and drive efficient issues resolution. Apply… more
- Google Inc. (Sunnyvale, CA)
- …Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This ... or equivalent practical experience. 4 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or mentor expedition.… more
- Theconstructsim (Milpitas, CA)
- 401(k) 401(k) matching Relocation bonus We are seeking a Senior Engineer , Package Design to work from our Milpitas, CA office. Responsibilities The Package ... substrate design focus on signal and power integrities analyses...high performance build-up substrates, flip chip assembly or 2.5D packaging . Knowledge and experience in extracting/simulating package designs for… more
- Apple Inc. (Santa Clara, CA)
- …job and there's no telling what you could accomplish!Our Hardware Technology Packaging team invents, designs, develops and integrates electronic packaging ... relevant industry experience Preferred Qualifications As the IC Package Design Engineer , you demonstrate fundamental knowledge or proven experience in the following:… more
- Advanced Technology Search (San Jose, CA)
- …including Enterprise and SMB. They are currently seeking a Hardware Systems Design Engineer responsible for taking a complex PCB system design through the entire ... as it is used on the complex PCB system's substrate . We also need someone who understands Signal and...overseas. This individual will also be cross-functional working with multiple groups in design, layout, test, SI/PI, and packaging .… more
- Eliyan (San Francisco, CA)
- …leading chiplet startup from the ground floor! As a Signal and Power Integrity Engineer , you will provide packaging solutions for chiplet interconnects in a ... design, modeling, manufacturing, assembly, and testing of traditional and advanced packaging for Eliyan's chiplet solutions. You will work with a cross-functional… more
- Google (Sunnyvale, CA)
- …Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This ... Package Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid**...experience. + 4 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or… more
- Northrop Grumman (Baltimore, MD)
- …Printed Wiring Boards (PWBs), and Circuit Card Assemblies (CCAs) using various substrate materials and chip-scale packaging technologies + Collaboration within a ... start + Experience with PWB/CCA design and signal routing, including chip-scale packaging technologies and substrate \PWB layout + Working knowledge of materials,… more
- Lockheed Martin (Goleta, CA)
- …polishing, substrate removal, or Anti\-Reflection \(AR\) coating or semiconductor packaging techniques\. * Must be a US Citizen, as this position is ... **Description:** You will be a Focal Plane Array Process Engineer with our Infrared Sensors Business on site in Goleta, CA\. Our team is responsible for developing… more
- SpaceX (Bastrop, TX)
- IC Package Engineer (Starlink/Akoustis) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. IC PACKAGE ENGINEER (STARLINK/AKOUSTIS) Akoustis is now operating as a wholly owned subsidiary of SpaceX,… more
- Broadcom (Irvine, CA)
- …Semiconductor Package Designer** **Role Overview** We are seeking an experienced IC Packaging Engineer to drive next-generation package architecture, design, and ... / assembly technologies. **Program Management & Cross-Functional Execution** + Own packaging deliverables from concept through substrate design, development,… more
- Applied Materials (Santa Clara, CA)
- …Process Engineer with deep experience in photonics and advanced packaging technologies to support the development of high-performance photonic interconnects and ... go. Learn more about our benefits (https://hrportal.ehr.com/applied/) . As a Process Engineer , you'll play a crucial role in designing and optimizing manufacturing… more
- NVIDIA (Santa Clara, CA)
- …on the world. We are seeking a passionate and experienced Senior Photonics Test Engineer who is committed to making a difference in the world through their ... labs and manufacturing sites. + Partner with internal design, fabrication, and packaging multi-functional teams to establish new test requirements, test flows, aid… more
- Micron Technology, Inc. (Boise, ID)
- …communicate and advance faster than ever. **Principal** **Signal Integrity** ** Engineer ** **- Interface Pathfinding** Micron's Interface Pathfinding team serves as ... opportunities for, and drive, performance scaling through innovative circuit, signaling, packaging and interconnect solutions with a 3-5 year outlook, and to… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Package Design Engineer in the Advanced Technology Group (ATG). NVIDIA's GPUs and SOCs are the world leaders in power, performance ... purpose, we are now seeking a passionate Package Design Engineer who is committed to making a difference in...Your responsibilities will include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design… more
