- Cadence Design Systems, Inc. (Austin, TX)
- …are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, ... of professional experience in SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT insertion flows +… more
- Microsoft Corporation (Hillsboro, OR)
- …manage and optimize the Cloud infrastructure. We are looking for a ** Senior Design for Test ( DFT ) Engineer ** to join the team. **Responsibilities** + ... experience. + 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test + ATPG, JTAG, Memory BIST, and trade-offs… more
- Microsoft Corporation (Raleigh, NC)
- …solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior DFT Engineer to join the team. **Responsibilities** + Execution ... across multiple projects, ensuring alignment with overall chip design goals. + Define and implement DFT ...chip design goals. + Define and implement DFT architecture, including scan insertion, boundary scan, MBIST, and… more
- Renesas (Austin, TX)
- Senior Staff DFT Engineer Job...to ATE + Coordinate with other Engineering disciplines + Design to ensure DFT approach is effective and ... datacenter. **What we need:** We are seeking a Mixed-Signal DFT Engineer to ensure efficient, high-coverage, testability...+ Ensure integrity in observability and controllability of each design block to/from the pins of the part +… more
- Celestica (Richardson, TX)
- …State/Province: Texas City: Richardson **Summary** We're searching for a dynamic and experienced Functional Design for Test ( DFT ) Engineer to join our team ... performance. + Drive insights through Functional DFT ( DFT -F) analysis, providing critical recommendations for design ...positive team with a balanced mix of young and senior experts + Various Celestica benefits: You will have… more
- SpaceX (Sunnyvale, CA)
- …extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. SOC/ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA...leveraging Siemens Tessent tools + Integration and verification of Design for Test ( DFT ) IPs and fabrics… more
- NVIDIA (Santa Clara, CA)
- …with 5+ years, MSEE with 3+ years, or PhD with 2+ years of experience in DFT , system architecture, or RTL design . + Understanding of fundamental DFT topics, ... Excellent understanding of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe… more
- NVIDIA (Santa Clara, CA)
- …imagination and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative ... solutions for DFT architecture, verification and post-silicon validation on some of...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power, to ensure we are… more
- Northrop Grumman (Linthicum Heights, MD)
- …to obtain and maintain an active clearance.** **Roles and Responsibilities:** + Responsible for DFT ( Design for Testabilty) aspects of ASIC Design thorough ... and Static Timing Analysis would be a plus + Active Clearance or higher ** Senior Principal Engineer Basic Qualifications:** + Bachelor's degree with 8 years of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... formal verification using JasperGold is a plus. + Deep expertise in DFT design , methodology, and implementation. + Familiarity with related domains such as… more
- General Motors (Warren, MI)
- …the role, it can be either _Warren, MI or Sunnyvale, CA as directe_ d. ** Design for Manufacturing, Testing, Tooling Engineer ** **The Role:** General Motors is at ... internal and external customers. **Responsibilities of the Design for Manufacturing, Design for Testing, Tooling Engineer include:** + Work with cross… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer ... Engineer , you will collaborate with RTL, Design for Testing ( DFT ), Floorplan, and full-chip Signoff ... practical experience. + 7 years of experience with physical design (eg from RTL to GDSII, including key stages...flows (eg, LEC, PI/SI, DRC/LVS, etc.). + Understanding of DFT including Scan, MBIST and LBIST. + Understanding of… more
- Northrop Grumman (Jessup, MD)
- …deliver remarkable new advantages to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital ... for both are listed below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + Bachelor's degree in a technical area (BSEE… more
- General Motors (Warren, MI)
- … design and development of our vehicle displays hardware. In this role, the Senior Hardware Design Engineer - Display Development will be responsible for ... for manufacturing (DFM), design for assembly (DFA), and design for testing ( DFT ) + Drive the validation and testing of hardware components and systems,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... expectations. + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until… more
- Microsoft Corporation (Hillsboro, OR)
- …a trusted experience to customers and partners worldwide and we are looking for a ** Senior Physical Design Engineer ** to help achieve that mission. The ... to Microsoft cloud hardware. We are looking for a ** Senior Physical Design Engineer ** with...block, subsystem, and top level. + Coordinate with CAD, RTL/ Design teams/ DFT , Architecture team, Foundry interface team,… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... to see: + MS/Phd in Electrical Engineering or Computer Engineer or related degree (or equivalent experience). + 5+...plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build cutting-edge ... that power everything from AI to gaming! As a Senior SOC Design Engineer , you'll...partnering with experts in ASIC design , Physical design , CAD, Package Design , Software, DFT… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering,...or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing… more
- Acuity Inc. (Fort Wayne, IN)
- …13,000 dedicated and talented associates. Visit us at www.acuityinc.com . **Job Summary** The Senior PCB Design Engineer and Altium Librarian is primarily ... Brands Lighting (ABL) and Acuity Intelligent Spaces (AIS), we design , manufacture, and bring to market products and services...of manufacturing processes. 7. Work with the manager and senior team members in Hardware Engineering to develop, track,… more