- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... the Team:** The Common Hardware Group (CHG) delivers the silicon , optics, and hardware platforms for Cisco's core Switching,...the RTL. + Work closely with the design/design-verification and PD teams to enable the integration and validation of… more
- NVIDIA (Santa Clara, CA)
- …see how you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What you'll be doing: + Work ... on SoC IP design, timing closure, power analysis, methodology alignment, and program execution, ensuring success from pre- silicon through post- silicon … more
- Voyant Photonics (New York, NY)
- …products out of cutting edge research in silicon photonics. Position Overview As a Senior Control Systems Engineer at Voyant, you will be at the forefront of ... range, velocity, and reflectivity with unparalleled accuracy. By leveraging cutting-edge silicon photonic chips smaller than your fingertip, we deliver sensors that… more
- Amazon (San Diego, CA)
- …underserved communities around the world. Come work at Amazon! The Role: As Senior SERDES Design Engineer , you will engage with an experienced cross-disciplinary ... collaborative peer environment. As a member of the Kuiper Silicon Development team, you will be responsible for the...(BIST, loopbacks, etc) - Familiarity with IP deliverables and PD (LEF, LIB, timing closure, EMIR, etc.) - Familiarity… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... clock/data alignment constraints. + Work closely with RTL and PD teams to extract clocking intent and drive accurate...Support timing closure and signoff through timing audits, and silicon correlation. What We Need To See: + Bachelor's… more
- Cisco (San Jose, CA)
- ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441220) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... our San Jose, CA office.** The Common Hardware Group (CHG) delivers the silicon , optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless… more
- Amazon (Cupertino, CA)
- Description Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create ... of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring… more