- Samsung Semiconductor (San Jose, CA)
- …business targets of Samsung in the future. We are seeking an experienced CPU Verification engineer to join our high-performance CPU design team. In this role, ... verification strategy for CPU design at cluster/unit level. Architect, develop UVM based cluster/unit level verification environment to verify functionality… more
- BCforward (Palo Alto, CA)
- …system Verilog, or matlab) * Strong DV background (test plan development, test writing, UVM ) * Experience with low power verification (UPF) * Experience with ... Silicon DD Engineer III BCforward is currently seeking a highly... * Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology) * Hands on… more
- GE Vernova (Imperial, PA)
- …Competent in hardware design tools: Altium Designer, PSpice; experience with verification methodologies including SystemVerilog and UVM Willingness to travel ... for technical collaboration, integration, and support activities Team-oriented, proactive, and receptive to diverse and fast-paced engineering environments Demonstrated autonomy and intellectual curiosity-ability to learn and apply new tools and architectures… more
- Draper (Boston, MA)
- …Summary: Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification ... generation of digital and embedded hardware platforms. + Develop verification and test plans + Develop UVM ...Develop verification and test plans + Develop UVM Agents for proprietary buses + Instantiate VIPs for… more
- Draper (Boston, MA)
- …Description Summary: Draper's Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification ... generation of digital and embedded hardware platforms. + Develop verification and test plans + Develop UVM ...Develop verification and test plans + Develop UVM Agents for proprietary buses + Instantiate VIPs for… more
- Draper (Boston, MA)
- …Summary: Draper's Digital Design Team is seeking a motivated and experienced Principal UVM Digital Verification Engineer to tackle novel verification ... + Strong analysis and problem-solving skills + Develop verification and test plans + Develop UVM Agents for proprietary buses + Instantiate VIPs for industry… more
- US Tech Solutions (Goleta, CA)
- …AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer , you will own functional ... and testing. **Mandatory:** + 8 years of experience with verification methodologies and languages such as UVM ...with verification methodologies and languages such as UVM and SystemVerilog. + Experience developing and maintaining … more
- Amazon (Redmond, WA)
- …networking and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating & Maintaining ...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based… more
- ManpowerGroup (Redmond, WA)
- **Job Title:** **Senior Verification Engineer - Networking & UVM ** **Location:** **Redmond, WA - Remote** **Employment Type:** **18 month contract** **About ... client, Global Leader in Technology is seeking a **Senior Verification Engineer ** to join our dynamic team...**Required Qualifications:** + 8-12 years of hands-on experience with ** UVM (Universal Verification Methodology)** + 8-12 years… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure.… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- NVIDIA (Santa Clara, CA)
- …CHI, ACE, ATB) and PCIe. We are specifically seeking a skilled ASIC Verification Engineer with deep knowledge of System Verilog, UVM , and C++, along with a ... NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next...implement constrained-random and directed testbenches using System Verilog and UVM to achieve verification closure. + Develop… more
- Northrop Grumman (Annapolis Junction, MD)
- …Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies into ... within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate… more
- Northrop Grumman (Linthicum Heights, MD)
- …career. We are looking for you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification Engineer based out of ... This requisition may be filled as a Principal Digital Engineer or a Senior Principal Digital Engineer ....complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. +… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
- ManpowerGroup (Santa Clara, CA)
- Our client, a leading technology firm, is seeking a Verification Engineer to join their team. As a Verification Engineer , you will be part of the design ... which will align successfully in the organization. **Job Title:** Verification Engineer **Location:** Santa Clara, CA **Pay... design verification . + Strong knowledge of UVM verification , DV tools & methodologies. +… more
- ManpowerGroup (Mountain View, CA)
- Our client, a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As a Silicon Verification Engineer , you ... mindset, which will align successfully in the organization. **Job Title:** Silicon Verification Engineer **Location:** Mountain View, CA **What's the Job?** +… more
- Meta (Austin, TX)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology 10. 2+ years… more
