- Cadence Design Systems, Inc. (San Jose, CA)
- … analysis , place and route, extraction, spice etc. Job Responsibilities: . Perform Static timing analysis , glitch, noise analysis , extraction using ... related field of VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows,… more
- SpaceX (Sunnyvale, CA)
- …solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at...(eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is required, ie; Genus, Fusion ... who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for… more
- The Boeing Company (Mountain View, CA)
- …Integrate DSP IP from Boeing's algorithm team and third-party IP as needed + Perform static timing analysis , LEC, CDC, linting, and other necessary checks to ... for multiple **ASIC and/or FPGA Design and Verification Engineers** at Lead, Senior & Principal levels to join us as part of our Boeing Electronic Products team… more
- Microsoft Corporation (Santa Clara, CA)
- …of low power microarchitecture techniques. knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis Silicon Engineering IC5 - The typical ... team within the Azure Hardware Systems & Infrastructure group is seeking a Principal Silicon Engineer. You will join our front-end silicon team and be responsible… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …design/EDA experienceStrong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is requiredPrior experience with ... Design Implementation and Signoff including Place and Route, Design Closure, and timing /power signoffGuide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Prior experience ... Preferred Good hands-on experience of Floorplanning , Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite Prior experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of ... fundamental physical design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …in writing and debugging RTL (Verilog, System Verilog). + Experience in RTL synthesis and static timing analysis is required. + Strong written and oral ... communication skills are required. + BS in EE/CS with 10+ years of work experience or MS in EE/CS with 4+ years of work experience required. + Some travel (up to 10% of time), including international travel, is required. The annual salary range for California… more