- Qualcomm (San Diego, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and...Tcl, Perl, or Python are also desirable. **Job Description: Principal Duties and Responsibilities** + Develop constraints for physical… more
- Cadence Design Systems, Inc. (Austin, TX)
- … analysis , place and route, extraction, spice etc. Job Responsibilities: . Perform Static timing analysis , glitch, noise analysis , extraction using ... related field of VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …includes RTL integration, maintain the timing constraint, Synthesis, Place and Route, Static timing analysis (STA), timing closure, power ... will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon bring up with the validation… more
- BAE Systems (Manchester, NH)
- …Vivado or Intel/Altera Quartus Digital simulation using Modelsim/Questa Significant experience with static timing analysis and clock domain crossing ... **Job Description** BAE Systems is seeking a Principal FPGA Design Engineer! See what you re...architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing and… more
- onsemi (Richardson, TX)
- …design concept to chip tape-out. Tasks include: + Verilog RTL coding + Design-for-Test + Static Timing Analysis in a variety of technologies + Logical and/or ... physical synthesis + UPF creation and low-power design + Analysis and design of complex timing and clock interfaces + IP integration, including analog content… more
- BAE Systems (Nashua, NH)
- …simulators + Working knowledge of internal logic analyzer (ILA/chipscope/signaltap) + Familiarity with static timing analysis tools and timing closure ... in design architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing, product support and FPGA… more
- Northrop Grumman (Dulles, VA)
- …FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power analysis + Experience ... . In this role, you will be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and… more
- Micron Technology, Inc. (Minneapolis, MN)
- …+ IP integration, + Clock tree design, + Place-and-route, + Constraint reviews, + Static timing analysis and signoff, + Physical verification, + Functional ... and outstanding opportunity. **Job Description** We're looking for a Principal Physical Design Engineer to join our team! In...and timing ECOs. **What you will be doing Daily** +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …will be focused on: + Enhancing and expanding the existing tools' architecture to cover timing analysis + Creating new frameworks for analysis of effects ... expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of...EDA tools and one or more of transistor level timing , power, noise, aging, reliability, and emir analysis… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …in writing and debugging RTL (Verilog, System Verilog). + Experience in RTL synthesis and static timing analysis is required. + Strong written and oral ... innovators who want to make an impact on the world of technology. Senior Principal Design Engineer - Systems and Interfaces San Jose Job Description: The Cadence… more
- RTX Corporation (Goleta, CA)
- …constructing testbenches to perform RTL simulation & verification, performing Synthesis, Static Timing Analysis , Place-and-Route, DFT (with use ... design, verification, validation, fabrication, packaging, debugging, test development, failure analysis , and documentation. You will work to develop new digital… more
- Honeywell (Plymouth, MN)
- …in multi-disciplinary teams + Background in BIST, Design For Test (DFT), physical synthesis, static timing analysis , and/or power analysis . + Direct ... + Lead efforts to map customer designs into Honeywell's ASIC technology + Timing constraints + Simulation + Conduct Code Synthesis + Test insertion and Test… more
- Cadence Design Systems, Inc. (Austin, TX)
- …industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Prior experience ... Preferred Good hands-on experience of Floorplanning , Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite Prior experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of ... fundamental physical design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with… more
- Cadence Design Systems, Inc. (Austin, TX)
- …design/EDA experience Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience ... backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure Experience in scripting languages such as Tcl/Perl/Python is… more
- Micron Technology, Inc. (Atlanta, GA)
- …a team + Experience with IP design/architecture + Knowledge of Verilog and static timing analysis + Excellent problem-solving and analytical skills ... + A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds + Having an innovative approach that is open to improving upon any of our processes or products. The US base salary range that Micron Technology estimates it… more
- Qualcomm (San Diego, CA)
- …Develop constraints for physical power aware synthesis, low power multi voltage domain checks, static timing analysis and power aware formal verification. + ... team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis , STA and CLP for premium tier chips. This is… more
- Micron Technology, Inc. (Minneapolis, MN)
- …optimization of Memory/Logic/Analog circuits. + Chip floor-planning, physical design, IP integration, static timing analysis , design validation, and required ... collaborative skills in this exciting and outstanding opportunity. We're looking for a Principal Physical Design Engineer (ASIC) to join our team! You will be… more