- NVIDIA (Santa Clara, CA)
- …team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. ... verification methodologies. + Contribute to architecting and developing brand-new RTL analysis flows. + Serve as an...documents and train internal users. + Use data collection, analysis , and reporting tools to provide methodology … more
- Cadence Design Systems, Inc. (Austin, TX)
- …with leading edge Wireless and Mobile Customers * Senior level Application Engineer position supporting RTL -to-GDS implementation flows using Encounter Digitial ... impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... digital implementation tools + Working closely with R&D on tools and methodology improvements + Create and contribute technical content for Cadence Online Support… more
- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and CAD teams to ... experience + Experience with Synthesis, place and route and signoff timing/power analysis . + Knowledge of high performance and low power implementation techniques +… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's ... (https://careers.google.com/benefits/) . + Develop, support, and execute implementation flows from RTL through GDS including some or all of the following: synthesis,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Power Optimization and Analysis Engineer ! NVIDIA prides ourselves in having energy efficient products. We believe that continuing ... NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate...internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve… more
- Meta (Austin, TX)
- …with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System ... Perform RTL Lint and work with the Designers to create waivers. 5. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 6. Perform Flat… more
- Micron Technology, Inc. (Atlanta, GA)
- …techniques **Preferred Qualifications:** + Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis . + ... world uses information to enrich life. As a Design Engineer at Micron Technology, Inc., you will be responsible...(Primetime) and the associated design flow. + Experience in RTL development for logic or mixed-signal circuits. **What Sets… more
- SpaceX (Sunnyvale, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX...teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +… more
- Meta (Sunnyvale, CA)
- …5. Perform RTL lint and work w/ designers to create waivers. 6. Perform RTL DFT analysis and improve DFT coverage for stuck-at faults. 7. Perform flat and ... to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm GPU Engineer , you may architect, design, implement, verify, and/or optimize the performance and power ... Engineering, or related work experience. **Job Description:** + Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu… more
- Siemens Digital Industries Software (Dallas, TX)
- …responsible for technical selling and support of PowerPro, a leading-edge platform for RTL /gate Power analysis and optimization. This includes, but is not ... required. Job Qualifications *5+ years of industry experience as an Applications Engineer or related field. *Proven hands-on ASIC RTL VHDL/Verilog/SystemVerilog… more
- Northrop Grumman (Linthicum, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug **Senior Principal Engineer Basic Qualifications:** + Bachelor's ... tools and techniques. The individual will perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level and SOC level using… more
- Qualcomm (Austin, TX)
- …on QUALCOMMs Adreno Graphics cores in the area of Low Power implementation and methodology . The Power Implementation Engineer will work in QUALCOMMs Adreno GPU ... will have responsibilities in one or more of the following areas: Power Analysis and Estimation, RTL and Synthesis Power Minimization, Power Intent design… more
- Qualcomm (San Diego, CA)
- …5nm, 4nm and below is highly advantageous + Prior experience in flow and methodology development is an advantage + RTL expertise (Verilog/System Verilog) + ... techniques to push PPA envelope which includes working with RTL design teams to optimize design. Incumbent is also...Genus/Innovus + Must have good knowledge of static timing analysis , reliability and power analysis + Strong… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... NVIDIA's designs + Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and circuits design, and timing and power convergence… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- Qualcomm (Santa Clara, CA)
- …**General Summary:** As a CAD Engineer focusing on the post silicon methodology and support, you will work with RTL , architecture, design, DV, software, ... low level HW/SW interaction and debug + Experience with RTL & Gate Level Simulations + Experience with power... & Gate Level Simulations + Experience with power analysis methodology **Principal Duties and Responsibilities:** *… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human inventiveness and intelligence. Are you a software engineer with a passion for hardware, ASIC design and VLSI? Be part of a ... diverse team crafting NVIDIA's chip design methodology ! We're responsible for NVIDIA's front-end ASIC...! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and… more