- Apple Inc. (Santa Clara, CA)
- … cache subsystem. Minimum Qualifications 10 + years of full time ASIC design experience in: Memory system development PPA (performance/power/area) analysis ... Cache design background including an understanding of different memory organizations and tradeoffs. Hands on Experience with multi-processor cache coherence… more
- Samsung Electronics GmbH (Mountain View, CA)
- …combination of education, training, and experience 3+ years of experience in SOC or ASIC design and architecture Prior direct academic and/or work experience in ... Senior Engineer , SoC Architect - Memory Subsystem Senior ...We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation… more
- Qualcomm (San Diego, CA)
- …languages is desired. Experience in designing RTL for GPU, CPU, DSP, Machine-Learning, cache , controller, video, display, camera blocks in ASIC is desired. ... all levels. What you will be doing Micro-architect and design RTL for blocks and modules of Adreno GPU...memory subsystem and interconnect, and power and system level design Identify advanced ways to optimize hardware design… more
- NVIDIA Corporation (Santa Clara, CA)
- …Posted Todayjob requisition id: JR2005335NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems ... Senior Memory System Engineer page is loaded## Senior Memory System Engineerlocations:...Cache , Memory controller and PHY.* Experience in the design , bring-up and validation for memory failure analysis* Experience… more
- Conductor (San Jose, CA)
- San Jose, California, United States Overview The ACD Design verification team independently verifies the ASIC designs against standardspecifications. This gives ... an unbiased view of ASICs as compared to the design engineers. This helps the designs to stick to...for great customer experiences. You will get involved in ASIC verification of the designs targeted for the wearables… more
- Apple Inc. (San Diego, CA)
- …of Apple device users. Our team is looking for an experienced software engineer with modern embedded C++ and Python skills and experienced in software‑defined‑radio ... system running on a heterogeneous computing system (CPU+FPGA, CPU+GPU, CPU+ ASIC accelerator, etc). Strong familiarity with low‑level systems programming using… more
- Apple Inc. (San Diego, CA)
- …of Apple device users.Our team is looking for an experienced software engineer with modern embedded C++ and Python skills and experienced in software-defined-radio ... system running on a heterogeneous computing system (CPU+FPGA, CPU+GPU, CPU+ ASIC accelerator, etc). Strong familiarity with low-level systems programming using… more
- NVIDIA (Santa Clara, CA)
- …design is preferred. + Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. ... As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and… more
- Micron Technology, Inc. (Richardson, TX)
- …communicate and advance faster than ever. Micron is seeking a highly motivated and experienced ASIC Design Engineer to define and drive the architecture of ... emerging non-volatile memory technologies. + Architect and model data path, control path, cache design , and IO interface logic for high-speed memory access and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group ... Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower...for Next generation SOC and Systems. + Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to… more
- Microsoft Corporation (Santa Clara, CA)
- …+ Understanding of cache coherency and memories + Software architectural and design sense Software Engineering IC4 - The typical base pay range for this role ... software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to… more
