- Apple Inc. (Santa Clara, CA)
- A leading technology company in Santa Clara seeks candidates experienced in ASIC design and high-performance memory subsystems. The ideal candidate should ... of 3 years of experience. Responsibilities include driving new memory system architectures and developing performance/power simulations. Competitive compensation… more
- Theconstructsim (Milpitas, CA)
- Front-End ASIC Design Engineer -...at least 2-3 of: CPU (ARM/RISC-V), GPU, DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; ... Industry 401(k) 401(k) matching Relocation bonus Job Title: Front-End ASIC Design Engineer Job Description (Milpitas, CA) Responsibilities Support… more
- Theconstructsim (Milpitas, CA)
- …Health insurance Paid time off Relocation bonus Vision insurance Job Title: Front-End ASIC Design Engineer - Milpitas, CA Responsibilities Support customer's ... design through all phases of ASIC execution at Socionext. Ensure designs meet product Performance‑Power‑Area‑Schedule...(preferably, ARM and/or RISC‑V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low‑power design and verification;… more
- Theconstructsim (Milpitas, CA)
- Job Title: Front-End ASIC Design Engineer Milpitas, CA Responsibilities Support customer's design through all phases of ASIC execution at Socionext. ... provided the work experience is solid micro-architecture and front-end design . Hands-on ASIC front-end design ,...(preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification;… more
- Theconstructsim (Milpitas, CA)
- Description We are seeking a Front-End SoC/ ASIC Design Engineer for our SoC business unit. Responsibilities Support customer's design through all phases ... provided the work experience is solid micro‑architecture and front‑end design . Hands‑on ASIC front‑end design ,...(preferably, ARM and/or RISC‑V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low‑power design and verification;… more
- Theconstructsim (Milpitas, CA)
- Front-End ASIC Design Engineer Milpitas, CA Description Milpitas, CA Benefits 401(k) 401(k) matching Relocation bonus Responsibilities Ensure designs meet ... provided the work experience is solid micro‑architecture and front‑end design . Hands‑on ASIC front‑end design ,...(preferably, ARM and/or RISC‑V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low‑power design and verification;… more
- Apple Inc. (Santa Clara, CA)
- …Hardware Description The ideal candidate will have experience in ASIC design with:- Architecture research and/or development of memory or highly ... memory subsystem, including dram controller, PHY architecture and design , DFI interface and dram interface calibration/training mechanisms and algorithms is… more
- Meta (Sunnyvale, CA)
- Summary Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part...to partner and collaborate with full stack software, hardware, ASIC Design , Emulation and Post‑Silicon teams towards… more
- Amazon (San Francisco, CA)
- Sr. ASIC Design Engineer , Cloud-Scale Machine Learning Acceleration team Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure ... rapid integration of emergent technologies. We're looking for an ASIC Design Engineer to help...attributes "Learn and Be Curious" mindset. Familiarity with accelerator design , interconnects, DMAs, memory sub‑systems, CPU cores,… more
- Apple Inc. (Santa Clara, CA)
- …of the cache subsystem. Minimum Qualifications 10 + years of full time ASIC design experience in: Memory system development PPA (performance/power/area) ... and controller which is part and parcel of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system… more
- SQL Pager LLC (San Jose, CA)
- …level micro-architectures, implementation, and validation Develop algorithmic computation engines, NAND memory controller, and so on Write up micro-architecture and ... design document and be able to present to customers Develop RTL, perform synthesis, lint and CDC check Working with customers to trouble shooting, debug, and tune… more
- Hewlett Packard Enterprise Development LP (San Jose, CA)
- ASIC Engineer Sr StaffThis role has...& Experience: 10+ years of hands-on DFT experience in ASIC design , preferably in networking or high-speed ... cutting-edge ASICs for next-generation networking platforms. We are looking for a seasoned** Design -for-Test (DFT) Engineer ** to join our team and contribute to… more
- NVIDIA Corporation (Santa Clara, CA)
- …Posted Todayjob requisition id: JR2005335NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior ... Senior Memory System Engineer page is loaded##... design .* Deep understanding and strong fundamental of memory design , features, ECC algorithm, SI and… more
- Qualcomm (San Diego, CA)
- …degree in Science, Engineering, or related field and 8+ years of ASIC design , verification, validation, integration, or related work experience. Master's ... Science, Engineering, or related field and 7+ years of ASIC design , verification, validation, integration, or related...computing, and high‑bandwidth memories such as HBM. Knowledge in memory controller design . Proficiency in use of… more
- Samsung Electronics GmbH (Mountain View, CA)
- Senior Engineer , SoC Architect - Memory Subsystem...and experience 3+ years of experience in SOC or ASIC design and architecture Prior direct academic ... Senior Engineer , SoC Architect - Memory Subsystem Job Location Mountain View, CA Job Category Job Type Full-Time Job # 402779 Job Department The Samsung Research… more
- Apple Inc. (San Diego, CA)
- …requirements while managing performance, power, and area trade‑offs. Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, ... CDC, RDC, Synthesis and STA. Preferred Qualifications Expertise in design domains such as memory subsystems, bus...design principles and associated CDC requirements. Familiarity with ASIC low power design techniques, including multiple… more
- Cadence Design Systems (San Jose, CA)
- Lead Applications Engineer DDR Design IP page is loaded## Lead Applications Engineer DDR Design IPlocations: SAN JOSEtime type: Full timeposted on: ... Technical Presales Engineer , you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence… more
- Cadence Design Systems (San Jose, CA)
- Senior Applications Engineer - DDR Design IP page is loaded## Senior Applications Engineer - DDR Design IPlocations: SAN JOSEtime type: Full timeposted ... an impact on the world of technology.** Senior Applications Engineer - DDR Design IP Job Location:...subsystem verification and/or performance analysis * Strong knowledge of ASIC flow, RTL design in Verilog, System… more
- nEye Systems, Inc. (Santa Clara, CA)
- …nEye's next‑generation optical switching platforms. This role complements our existing ASIC design leadership by focusing on embedded controller architecture, ... enhanced performance, efficiency, and scalability. Role Overview We're seeking a Lead Hardware Engineer to drive the design and development of advanced digital… more
- Cadence Design Systems (San Jose, CA)
- …innovators who want to make an impact on the world of technology.**We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ... Verilog testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for… more
