• IC Packaging , Principal AE

    Cadence Design Systems, Inc. (San Jose, CA)
    …of the Cadence tool set in the context of multiple flows including IC Packaging , high speed design, signal integrity and electrical constraints definition. ... Design experience and industry knowledge of current IC Packaging Design and manufacturing processes is required. Knowledge of advanced IC packaging flows… more
    Cadence Design Systems, Inc. (06/08/25)
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  • Principal IC Packaging Engineer,…

    SpaceX (Bastrop, TX)
    Principal IC Packaging Engineer, Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... with the ultimate goal of enabling human life on Mars. PRINCIPAL IC PACKAGING ENGINEER, SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its experience in… more
    SpaceX (07/15/25)
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  • Sr. IC Packaging Engineer, Silicon…

    SpaceX (Bastrop, TX)
    Sr. IC Packaging Engineer, Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... with the ultimate goal of enabling human life on Mars. SR. IC PACKAGING ENGINEER, SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its experience in building… more
    SpaceX (07/15/25)
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  • Sr. IC Packaging Test Engineer,…

    SpaceX (Bastrop, TX)
    Sr. IC Packaging Test Engineer, Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring ... with the ultimate goal of enabling human life on Mars. SR. IC PACKAGING TEST ENGINEER, SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its experience in… more
    SpaceX (07/15/25)
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  • IC Packaging Test Engineer, Silicon…

    SpaceX (Bastrop, TX)
    IC Packaging Test Engineer, Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... possible, with the ultimate goal of enabling human life on Mars. IC PACKAGING TEST ENGINEER, SILICON TECHNOLOGY (STARLINK) Starlink believes in providing fast,… more
    SpaceX (07/15/25)
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  • Portfolio Manager - Integrated Circuit…

    3M (Maplewood, MN)
    …the world. We are looking for a results-oriented Global Portfolio Manager for IC Packaging Materials to drive Semiconductor business growth and segment expansion ... team. Here, you will make an impact by: **Global Portfolio Management responsibility for IC Packaging Materials Solutions, including but not limited to:** + Lead… more
    3M (07/12/25)
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  • Product Marketer - Integrated Circuit…

    3M (Maplewood, MN)
    …the world. We are looking for a results-oriented Global Product Marketer for IC Packaging Materials to drive Semiconductor business growth and segment expansion ... you will make an impact by: **Global Product Marketing responsibility for IC Packaging Materials Solutions, including but not limited to:** + Develop and execute… more
    3M (07/22/25)
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  • 3DIC Packaging SI/PI Applications Engineer

    Siemens (Irvine, CA)
    …in this strategic role and help pave the way for the future of 2.5D/3D IC packaging analysis with Siemens technology, all while helping engineers solve today's ... Power Integrity and EM products focused on the area of 2.5D/3D IC heterogenous packaging . You'll work collaboratively with a wide range of customers from… more
    Siemens (07/04/25)
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  • NCG Staff Engineer, Packaging Engineering…

    SanDisk (Milpitas, CA)
    …Proficient in product management and strong knowledge of material properties used in IC packaging + Familiarity with statistical tools and failure analysis ... moving forward. **Job Description** We are seeking a highly skilled Staff Engineer, Packaging Engineering to join our team in Milpitas, United States. In this role,… more
    SanDisk (07/26/25)
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  • Principal Engineer, Packaging Engineering

    SanDisk (Milpitas, CA)
    …through academic coursework or experience required in thermal modeling and measurements of IC packaging and related areas. + A strong background in thermal ... **Job Description** ESSENTIAL DUTIES AND RESPONSIBILITIES: + As a Packaging Engineer, you will work in the Packaging... Packaging Engineer, you will work in the Packaging R&D group on thermal designs across semiconductor … more
    SanDisk (05/31/25)
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  • Design Engineer, Senior Director

    Applied Materials (Santa Clara, CA)
    …Stay updated on industry standards, materials, and technologies relevant to 3D IC packaging . + Problem Solving: Identify and address design-related issues ... Engineering, Physics, or a related field. + Experience: Proven experience in IC packaging design, with expertise in 3D packaging technologies and… more
    Applied Materials (05/10/25)
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  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …with focus on Advanced IC Package Routing, Technologies, and Flows. As an IC Packaging Product Engineer, you will be responsible for driving innovation and ... expanding Cadence IC Packaging Advanced Routing and Automated Solutions leadership, tackling the complex substrate interconnect challenges of advanced package… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Systems Design/Architecture Engineer

    Teledyne (Garland, TX)
    …background, for customer interface with knowledge base of semiconductor electronics, IC packaging and hybrid modules. **Essential Duties and Responsibilities:** ... boards (Evaluation kits) which will require understanding of customer application + Packaging concepts such as ceramics and hybrid modules. Including assessment of… more
    Teledyne (07/04/25)
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  • SMT Technician, Semiconductors (Starlink)

    SpaceX (Hawthorne, CA)
    …assembly in-house for development and manufacturing. You will work closely with IC packaging engineers, equipment manufacturers, and leadership. The success of ... operations and processing of microelectronic products + Operate semiconductor and packaging equipment in a cleanroom environment + Product handling using best… more
    SpaceX (06/21/25)
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  • Display Silicon Architect

    Google (Mountain View, CA)
    …of pixel architectures and driving schemes for active displays. + Knowledge of IC manufacturing, advanced packaging and their impact on design, with excellent ... working in display-related silicon chip design, with digital, analog, and IC designs. + Experience with product development for consumer electronic applications.… more
    Google (07/09/25)
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  • Software Engineer (C++, Numerical Analysis, EDA)

    Cadence Design Systems, Inc. (Boston, MA)
    …your favorite tablet. Responsibilities: * Design and develop advanced automated design flows for 3D- IC , IC Packaging and PCB applications* Design and develop ... cutting-edge placement and power solutions, focusing on the advanced manufacturing technologies and solution automation* Apply excellent knowledge of object-oriented paradigm, data structures and algorithms, as well as good communication skills and a… more
    Cadence Design Systems, Inc. (07/04/25)
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  • Sr. Global Commodity Manager, Devices Supply Chain…

    Amazon (Sunnyvale, CA)
    …in supplier/supply chain management, with strong knowledge of the semiconductor industry, IC manufacturing and packaging processes and key suppliers. - ... commercial assessment of emerging foundry technologies, IP portfolios, and advanced packaging solutions to support Amazon's silicon innovation roadmap - Manage… more
    Amazon (07/22/25)
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  • Sr. IC Layout Designer (Silicon…

    SpaceX (Irvine, CA)
    Sr. IC Layout Designer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. SR. IC LAYOUT DESIGNER (SILICON ENGINEERING) At SpaceX we're leveraging...power and ground distribution as well as working with packaging engineer to determine pad locations + Accurately estimate… more
    SpaceX (06/18/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …layout engineers to optimize layout for area and performance + Work with CAD, packaging and foundry teams in resolving layout and / or verification issues + ... Experience required on technologies: 40nm, 16nm / 7nm FinFet -Knowledge of I/O, ESD, packaging , CAD setup, Cadence SKILL and Unix scripting is a plus -A team player,… more
    Broadcom (07/26/25)
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  • Integrated Circuit ( IC ) Layout and Mask…

    MIT Lincoln Laboratory (Lexington, MA)
    …fabrication (eg, silicon, compound-semiconductor, wafer bonding, flip-chip hybrid), packaging , and testing of electronic and photonic circuits. These ... deposition (CVD)) and fabrication * Microsystems Integration Facility (MIF): Packaging and integration facilities for wire-bonding, vacuum-reflow soldering, flip-chip… more
    MIT Lincoln Laboratory (05/29/25)
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