• Low Power ASIC

    NVIDIA (Santa Clara, CA)
    …make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2025. We continue to rapidly ... to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI,… more
    NVIDIA (08/01/25)
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  • ASIC FPGA Design and Verification…

    The Boeing Company (Mountain View, CA)
    …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. And we're applying the latest...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC more
    The Boeing Company (07/26/25)
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  • ASIC Engineer , Formal Verification

    Meta (Boston, MA)
    …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 22. Experience with development of… more
    Meta (08/01/25)
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  • ASIC Engineer , Formal Verification

    Meta (Sunnyvale, CA)
    …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 21. Experience with development of… more
    Meta (08/01/25)
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  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …Memories 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with low power techniques for reducing power 22. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
    Meta (08/01/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...management, and post-synthesis ECO flows. + Solid background in low - power and high-performance design optimization techniques. +… more
    NVIDIA (07/01/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
    Amazon (07/10/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …Tcl scripting skill Other highly desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The ... challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from… more
    Broadcom (07/26/25)
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  • Sr. ASIC Modem Design Engineer

    Amazon (Sunnyvale, CA)
    …communities around the world. Come work at Amazon! We're hiring a Sr. Modem Design Engineer within a high performance ASIC design team. This team is using ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to chip specification to RTL to optimizing timing / power to chip level validation. . Develop solutions optimizing… more
    Amazon (07/12/25)
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  • ASIC Design Efficiency Engineer

    NVIDIA (Santa Clara, CA)
    …crowd: + Pipeline processor or deep learning accelerator design/architecture experience + Low power or physical (synthesis/VLSI) design experience + Scripting ... We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is...and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements. + Execute and deliver… more
    NVIDIA (06/27/25)
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  • Senior ASIC Design Engineer , Kuiper…

    Amazon (Austin, TX)
    …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband… more
    Amazon (06/27/25)
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  • ASIC Design Engineer , Kuiper…

    Amazon (Austin, TX)
    …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband… more
    Amazon (07/30/25)
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  • Principal ASIC Verification Engineer

    Amazon (North Reading, MA)
    …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology....using test benches, which can be reused for the ASIC implementation - Run formal verification of complex blocks… more
    Amazon (07/24/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …will be doing: + You will drive physical design and timing of high-frequency and low - power DPUs and SoCs at block level, cluster level, and/or full chip level. ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
    NVIDIA (05/14/25)
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  • Senior ASIC Design Engineer

    Amazon (San Diego, CA)
    …. Experience with products that have gone to volume production . Experience in low power design techniques Preferred Qualifications . Master's or Ph.D degree in ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing… more
    Amazon (07/09/25)
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  • Sr. ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities -Define architecture specifications based on requirements… more
    Amazon (07/19/25)
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  • Sr. CAD Engineer , ASIC

    Amazon (Austin, TX)
    Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband ... Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining...experience with emphasis on methodology and best practice - Power estimation and optimization - Back end tool experiences… more
    Amazon (07/10/25)
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  • ASIC Verification Engineer

    Amazon (Sunnyvale, CA)
    …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block… more
    Amazon (06/04/25)
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  • ASIC Physical Design Engineer

    Amazon (Austin, TX)
    …which is a machine learning inference accelerator designed to deliver high performance at low cost. If this sounds exciting to you - come build the future with ... in various aspects of physical design: full chip floorplanning, circuit analysis, power /clock distribution, timing optimization, place and route, power integrity… more
    Amazon (06/17/25)
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  • Senior Low Power Integration…

    NVIDIA (Santa Clara, CA)
    …a member of this team, you are responsible for developing and validating system level low power features with a deep understanding of products needs that will ... you will be doing: + Bring up system level low power features to address existing and...lab tools (oscilloscopes, multimeters, logic analyzers). + Experience with ASIC power saving features and methods +… more
    NVIDIA (06/03/25)
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