- Chelsea Search Group (Richardson, TX)
- …low-power designs including physical-aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification ... Senior Physical Design Engineer Full-time +...Bus/Pin variables, Synthesis, Place and Route Optimization, Parasitic Extraction, Static Timing Analysis, Low Power Intent (UPF/CPF),… more
- Google (Sunnyvale, CA)
- …Science, a related field, or equivalent practical experience. + 5 years of experience in static timing analysis. + Experience in full chip timing sign-off ... ASICs. + Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug. Preferred qualifications: + Experience writing, reviewing and… more
- Northrop Grumman (Morrisville, NC)
- …work of your career. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, ... an active DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for static timing analysis on digital designs to ensure timing requirements… more
- NVIDIA (Westford, MA)
- …+ Experience in critical path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join...in full-chip/sub-chip Static Timing Analysis (STA), timing … more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints… more
- NVIDIA (Santa Clara, CA)
- …or related field (or equivalent experience). + 6+ years of experience in static timing analysis, methodology, or constraint development. + Strong expertise in ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing methodologies.… more
- NVIDIA (Austin, TX)
- …Engineering or Device Physics (or equivalent experience) + 8+ years experience in gate-level static timing analysis and/or power analysis + Proficiency in C++ + ... algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale...algorithms for large scale and high accuracy gate-level power, timing , parasitic, and noise analysis. A deep understanding of… more
- Microsoft Corporation (Austin, TX)
- …domain. + Facilitate coordination across cross-functional teams, including DFT, RTL/Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power & ... optimize the Cloud infrastructure. We are looking for a ** Senior Physical Design Engineer ** to join the...including DFT modes and methodologies, with comprehensive experience in Static Timing Analysis (STA) for complex hierarchical… more
- NVIDIA (Santa Clara, CA)
- …EE background with an in-depth understanding of circuits, simulation, library characterization and static timing analysis? Enjoy working on the cutting edge of ... We are now hiring for a Senior Library Design Engineer ! NVIDIA has...advanced process nodes + Hands-on experience with standard cell timing , power, statistical characterization and modeling. Familiar with advanced… more
- NVIDIA (Santa Clara, CA)
- …distribution, chip assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end verification. What we ... We are now looking for a Senior Physical Design Engineer . NVIDIA has...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD… more
- Cisco (San Jose, CA)
- …working with Verilog or System Verilog programming skills + Experience with simulators/synthesis/ static timing constraints and related tools (eg, VCS, DC, ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806)...participate in reviews. + Implement Verilog RTL to meet timing , performance, and power requirements. + Contribute to full… more
- NVIDIA (Santa Clara, CA)
- …+ Place and route tool experience with Synopsys ICC2 or Candence Innovus + Static timing analysis with Synopsys Primetime. + Understanding of DFT and multi-mode ... on power grid planning, Clock tree Synthesis (CTS) and timing closure. + Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM… more
- L3Harris (Camden, NJ)
- …and perform module level simulations + Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA) + Perform RTL quality using: Lint, Reset Domain ... in the interest of national security. Job Title: Sr ASIC/FPGA VHDL Design Engineer Job Code: 24260 Job Location: Camden, NJ-relocation available for those that… more
- Microsoft Corporation (Santa Clara, CA)
- …Domain Crossing design techniques. + Proficiency in Verilog, System Verilog, Synthesis and Static Timing Analysis. + Self-motivated and able to work effectively ... Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our...Collaborate with Physical design teams to ensure design meets timing and area requirements. + Work on post-silicon verification… more
- Microsoft Corporation (Raleigh, NC)
- …that will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Silicon Logic Design Engineer ** to join the team. **Responsibilities** In ... functional block RTLs into SoC RTL + Performing design quality checks such as timing closure, lint, CDC, synthesis, and low power intent + Collaborating with the… more
- Microsoft Corporation (Redmond, WA)
- …that will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Fabric Design** ** Engineer ** to join the team. **Responsibilities** + Be ... all aspects of the design flow including microarchitecture, RTL coding, Lint, CDC, timing closure, etc + Collaborate with team members to define interfaces and make… more
- Cisco (San Jose, CA)
- …+ DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis + Post silicon validation using DFT patterns. **Why ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) +...experience (DFT + Debug logic/features) + Prior exposure to LINT/CDC/ timing constraints/etc + Verilog design experience - developing custom… more
