- Draper (Cambridge, MA)
- …Description Summary: Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel ... and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal...of digital and embedded hardware platforms. Develop verification and test plans Develop UVM Agents… more
- Draper (Boston, MA)
- …Description Summary: Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel ... and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal... digital and embedded hardware platforms. + Develop verification and test plans + Develop UVM … more
- Northrop Grumman (Linthicum Heights, MD)
- …of your career. We are looking for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer ... NC. This requisition may be filled as a Principal Digital Engineer or a Senior Principal ...our cross-discipline engineering team in Mission Systems that encompasses Digital Verification Engineering to support ASIC and… more
- Northrop Grumman (Mcclellan, CA)
- …**a Full Top Secret/SCI security clearance with Polygraph** **.** **Basic Qualifications Senior Principal Digital Verification Engineer:** + Bachelor's ... Secret/SCI security clearance with Polygraph** **.** **Preferred Qualifications Principal / Senior Principal Digital Verification Engineer:** + Advanced… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... choice to join our diverse team today! As a Senior Digital Design Verification Engineer...models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM . + Build… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …Engineering, Computer Science, or a related field * Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, ... short video: https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies...etc. * UVM concepts * Directed, constrained-random, and assertion-based … more
- Huntington Ingalls Industries (Roanoke, VA)
- …Engineering, Computer Science, or a related field * Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, ... short video: https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies...etc. * UVM concepts * Directed, constrained-random, and assertion-based … more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level Digital Design Verification engineer. In this highly ... PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in digital design verification + Hands on experience in SV UVM , SV RNM and … more
- BAE Systems (Westminster, CO)
- …scripting languages (eg Ruby, Python, TCL). + Experience in documentation and verification of high-speed digital electronics, FPGAs, and embedded processor ... incentives may be available based on position level and/or job specifics. ** Senior FPGA Verification Engineer** **110106BR** EEO Career Site Equal Opportunity… more
- Tarana Wireless (Milpitas, CA)
- …that you will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate ... as Python What You'll Need: + BSEE required/MSEE preferred + 5-12 years of related Verification experience + Strong knowledge of UVM + Proficiency with at least… more
- Amazon (Boise, ID)
- …with team members across multiple disciplines - Deliver detailed test plans for verification of complex digital design blocks by working with design engineers ... and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. - Identify and write all types of… more
- Capgemini (Santa Clara, CA)
- **About the job you're considering** We're looking for a collaborative Senior Mixed-Signal Design Verification Engineer to help shape the future of SoC ... continuous learning, and innovative problem-solving. **Your role** + Develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs… more
- BAE Systems (Austin, TX)
- …growing your skills, and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)**… more
- Amazon (San Diego, CA)
- …Master's or Ph.D degree in Electrical / Communications Engineering * 10+ years in digital verification * Hands on experience working closely with Systems team on ... * Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM , System C and DPI-C *… more
- The Boeing Company (Fairfax, VA)
- …Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part of ... low SWAP-C flight computers. And we're applying the latest digital IC design processes with industry-best tools to enable...is a unique time where we're hiring design and verification engineers at every level as we're only limited… more
- Capgemini (Austin, TX)
- …Job You're Considering** We are seeking a seasoned and collaborative **SoC** **Design Verification Lead Engineer** to join our dynamic team. In this role, you'll ... lead verification efforts across complex SoC projects, mentor fellow engineers,...SystemVerilog, Verilog-HDL, and C-shell scripting. + Strong expertise in UVM /OVM, SystemVerilog Assertions, and functional coverage. + Proven SoC… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... voltage regulation and silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced … more
- Qualcomm (San Diego, CA)
- …will plan, design, optimize, verify, and test electronic systems, validate digital /analog designs and develop a comprehensive validation/ verification testbench ... Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As… more
- Microsoft Corporation (Redmond, WA)
- …and Low Power Verification . + Define and implement efficient UVM -based verification environments and use them to verify+test digital designs + Test plan, ... engineers around the world. We are looking for a ** Senior Quantum Engineer - Cryo-CMOS Digital Circuit...+ Knowledge of verification principles, testbenches, Universal Verification Methodology ( UVM ), and coverage. + Experience… more
- Northrop Grumman (Annapolis Junction, MD)
- …engineers to make these technologies a reality. **What You'll Get To Do:** As a Digital Verification Lead Engineer, you will have an opportunity to be a part ... encouraged, all within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The… more
