- Cisco Systems Inc (San Jose, CA)
- …Experience with block/full chip SDC development in functional and test modes Experience in Static Timing Analysis and prior working experience with STA tools ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- Qualcomm (Austin, TX)
- …designers, and provide feedback on power, timing , and area. Perform logic synthesis, early static timing analysis and early power analysis for the ... designs before the full implementation cycle. Evaluate all aspects of the design process from instruction set architecture to implementation. Use system tools such as digital design simulator, design synthesis engine, power estimation engine, etc. Troubleshoot… more
- Red Cell Partners (Torrance, CA)
- …Cadence tools and standard cell libraries. Support ASIC tape-out activities, including synthesis, static timing analysis , and design signoff. After silicon ... About The Role We are seeking a motivated and detail-oriented Digital Design Engineer to join our team in the development of digitally controlled power management… more
- Google (Sunnyvale, CA)
- …Science, a related field, or equivalent practical experience. + 5 years of experience in static timing analysis . + Experience in full chip timing ... for ASICs. + Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug. Preferred qualifications: + Experience writing, reviewing and… more
- Northrop Grumman (Morrisville, NC)
- …work of your career. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, ... maintain an active DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for static timing analysis on digital designs to ensure timing … more
- Meta (Sunnyvale, CA)
- …Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- Meta (Austin, TX)
- … timing analysis , SI noise analysis 11. Experience with running Static Timing Analysis for full chip using DMSA 12. Knowledge of front-end and ... experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip… more
- NVIDIA (Santa Clara, CA)
- …years experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …+ 8+ years experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...+ You will be responsible for all aspects of timing including, timing analysis and… more
- NVIDIA (Westford, MA)
- … tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon...be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. + Experience in Static Timing Analysis and prior working experience with STA tools ... ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US +… more
- NVIDIA (Austin, TX)
- …Engineering or Device Physics (or equivalent experience) + 8+ years experience in gate-level static timing analysis and/or power analysis + Proficiency ... algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale...algorithms for large scale and high accuracy gate-level power, timing , parasitic, and noise analysis . A deep… more
- SanDisk (Milpitas, CA)
- …entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis , logic equivalence, DFT insertion, place-and-route, ... of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory...clock tree synthesis, extraction, static timing analysis , physical verification)… more
- Cadence Design Systems, Inc. (Austin, TX)
- …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... seminars within Cadence and customer sites. Requirements; 10+ years of experience in Static timing analysis , Individual should be able to lead and execute… more
- Northrop Grumman (Annapolis Junction, MD)
- …to obtain and maintain a TS/SCI clearance.** **Preferred Qualifications:** **Strong background in static timing analysis and timing characterization ... to obtain and maintain a TS/SCI clearance.** **Preferred Qualifications:** **Strong background in static timing analysis and timing characterization… more
- Meta (Sunnyvale, CA)
- …Perf/W, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis , IR drop, EM, and physical ... and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical...H-Tree, and clock power reduction techniques 20. Knowledge of static timing analysis and concepts,… more
- Micron Technology, Inc. (Richardson, TX)
- …expertise in design optimization for performance and low power consumption, including UPF, static timing analysis , synthesis design constraints, and closing ... the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design and develop next-generation HBM DRAM products. You… more
