• DFT Engineer (Server)

    Qualcomm (San Diego, CA)
    EDA ATPG and insertion tools. + Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis. **Minimum Qualifications:** * ... who will be responsible for the implementation and verification of advanced DFT /DFD (Design for Test/Design for Debug) techniques for low power, multi voltage… more
    Qualcomm (04/08/25)
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  • DFT Methodology - Data Analytics…

    NVIDIA (Santa Clara, CA)
    … topics, such as, fault modeling, ATPG and fault simulation + Experience in application of AI for EDA -related problem-solving + Good understanding of technology ... NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
    NVIDIA (06/12/25)
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  • Product Engineer Silicon Debug - US

    Siemens (Wilsonville, OR)
    …division seeks a highly motivated, creative, and energetic individual as Product Engineer , specializing in design-for-test ( DFT ) and test delivery/debug at chip ... as user and reference manuals + Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and… more
    Siemens (06/13/25)
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  • Senior Software Engineer - ATPG - Tessent

    Siemens (Wilsonville, OR)
    …Job Description: We are looking for a highly motivated and capable software engineer to join the R&D team developing the automatic test pattern generation (ATPG) ... Knowledge of design flow aspects, including the logic synthesis, DFT , ATPG, simulation, formal and timing verification. + Solid...test industry practices. + Experience in using or developing EDA tools. Why us? Working at Siemens Software means… more
    Siemens (06/01/25)
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  • Senior Physical Design Engineer , Static…

    Google (Sunnyvale, CA)
    …and timing ECO creation, timing margins). + Experience with Electronic Design Automation ( EDA ) tools (ie, Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl ... In this role, you will work on the physical implementation of Application -specific integrated circuits (ASIC) using advanced technology nodes. You will work on… more
    Google (06/13/25)
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  • Library Characterization and Timing Methodology…

    Qualcomm (San Diego, CA)
    …know-how and hands-on experience and automation skills. Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation ... Verilog views and tools. Silicon reliability modeling, validation with multiple foundries & EDA house is a plus. **Required for this Role:** + Strong Std cell… more
    Qualcomm (06/09/25)
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  • SOC/ASIC Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
    SpaceX (04/15/25)
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  • Sr. SOC/ASIC Physical Design Engineer

    SpaceX (Bastrop, TX)
    Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
    SpaceX (04/15/25)
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  • Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... performance at low cost. You'll provide leadership in the application of new technologies to large scale deployments in...- Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies… more
    Amazon (06/03/25)
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  • ASIC Physical Design Engineer Intern,…

    Amazon (Austin, TX)
    …hours/week) for 12 consecutive weeks during summer. By applying to this position, your application will be considered for all locations we hire for in the United ... physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic...with Place and Route, digital implementation - Experience with EDA tools from Synopsys (ICC2, DC, PT), Cadence (Genus,… more
    Amazon (05/16/25)
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  • GPU Physical Design Engineer

    Qualcomm (San Diego, CA)
    …power, and packaging teams to ensure holistic design convergence + Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows ... and its sub-blocks + Hands on experience with Synthesis, DFT , Place and Route, Timing and Reliability Signoff +...with a disability and need an accommodation during the application /hiring process, rest assured that Qualcomm is committed to… more
    Qualcomm (05/28/25)
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