- Cisco (San Jose, CA)
- …of engineers to complete verification of a complex block, cluster or chip-level design * Lead verification for a complete SOC or ASIC i * Prior Experience with ... working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact: You will gain...You will: * Architect block, cluster and top level DV environment infrastructure * Create DV infrastructure… more
- Qualcomm (Santa Clara, CA)
- …milestone planning & critical debugs + Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV methodologies (formal, simulation, ... As a Design Verification Lead , you will lead a team of ASIC design verification...plus + 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification… more
- Meta (Sunnyvale, CA)
- …test program development 18. Familiar with IP, sub-system and SoC DV to execute DV working with DV lead 19. Some familiarity with compute and/or memory ... research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ ASIC solutions to enable in-system testing and prototyping. The goal is to… more
- Meta (Sunnyvale, CA)
- …collaboration on low power/high performance IP/SOC projects 9. 2+ years of Management or Technical leadership experience 10. 6+ years of System Verilog UVM DV ... with assertions (SVA) or others 12. Knowledge of digital ASIC design flows, project management and milestones 13. Knowledge...DSP coding and optimization 22. Experience to collaborate and/or lead in a team environment 23. PhD in Electrical… more
Locations:
California,
Washington