• Chip Integration Engineer

    Broadcom (San Jose, CA)
    …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The ... and routing ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks, soft/hard IPs, IOs, and… more
    Broadcom (11/19/25)
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  • Sr. Full Chip Physical Design…

    SpaceX (Sunnyvale, CA)
    …flows as needed to meet the overall design quality of results and chip integration requirements BASIC QUALIFICATIONS: + Bachelor's degree in electrical ... Sr. Full Chip Physical Design Engineer (Silicon Engineering)...chip floorplan reviews and identify area, interconnect, IP integration , and floorplan improvement opportunities + Perform chip more
    SpaceX (11/14/25)
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  • Silicon Photonics Chip Assembly & Packaging…

    Global Foundries (Malta, NY)
    …+ Experience completing failure analysis, design of experiments, & packaging process integration . + Expertise in chip package interaction for 2D, 2.5D, ... information, visit www.gf.com . Summary of Role: This hands-on Package and chip assembly Engineering role will develop industry leading advanced packaging utilizing… more
    Global Foundries (10/23/25)
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  • Design Engineer - Chip Floorplanner

    Broadcom (Fort Collins, CO)
    …through production. **Role Overview** This Floorplanning Engineer role focuses on chip -level physical architecture and integration for advanced ASICs in deep ... to ensure clean tapeout readiness. + Coordinate with block owners and integration teams for smooth block-level to top-level convergence. + Support cross-functional… more
    Broadcom (11/12/25)
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  • Chip Architect

    Texas Instruments (Dallas, TX)
    …the chip architecture to meet all project requirements. + Own the chip top-level integration . Drive the integration process from architectural definition ... to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan. **Why TI?** + Engineer your future. We… more
    Texas Instruments (11/07/25)
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  • Sr.System Integration & Test…

    Amazon (El Segundo, CA)
    …that result in a positive impact on a global scale. The Sr. System Integration & Test (I&T) engineer will engage with an experienced cross-disciplinary team ... and test innovative space-based and terrestrial applications. The System I&T Engineer will work closely with colleagues throughout Amazon Leo Government (ALG)… more
    Amazon (09/23/25)
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  • Senior Test and Integration Engineer

    Leidos (Linthicum, MD)
    **Description** Leidos is currently looking to add a Test and Integration Engineer to a Cyber Security Program near Ft. Meade, MD. This challenging position ... complex, mission-critical Program. The successful candidate willperform the installation, integration , and test of operational equipment/software to verify compliance… more
    Leidos (11/07/25)
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  • Mixed-signal ASIC Design and Integration

    IBM (Yorktown Heights, NY)
    …advanced high-performance circuits in advanced node for exploratory applications * Chip integration experience leveraging mixed-signal analog-on-top (AoT) or ... applications. Experience with mixed-signal analog-on-top (AoT) or digital-on-top (DoT) integration design flows that leverage EDA-driven digital circuit design… more
    IBM (11/07/25)
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  • Post Silicon Hardware System Integration

    NVIDIA (Santa Clara, CA)
    …and help define the future of computing. We seek an experienced Post-Silicon Hardware Engineer to join our Silicon Solutions Group. In this role, you will validate ... meet aggressive schedules. + Cross-Functional Impact - Partner with architects, chip /board designers, firmware/software engineers, and QA to drive design, debug, and… more
    NVIDIA (11/05/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased over the years. We are now packing tens of ... The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration , and chip build and assembly. You should be… more
    NVIDIA (11/20/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …definition and design of Computer Vision/Image Sensing IP. 2. Contribute to chip -level integration , verification plan development and verification. 3. Define ... static timing analysis. 4. Support the test program development, chip validation and chip life until production...8. 7+ years of experience as a Digital Design Engineer 9. Experience with top level integration more
    Meta (10/30/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …or block level uArchitecture definition and RTL implementation 2. Contribute to chip -level integration , verification plan development and verification 3. Define ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...static timing analysis 4. Support the test program development, chip validation and chip life until production… more
    Meta (10/18/25)
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  • Principal Embedded Software Engineer

    RTX Corporation (Atlanta, GA)
    …+ Designed and implemented software for embedded microprocessors and system-on- chip (SoC) architectures, including integration with FPGA-based systems, ... Sub-System Products Department is currently seeking a Principal Embedded Software Engineer for the Advanced Front-End Hardware organization in Atlanta, GA. You… more
    RTX Corporation (10/26/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and ... AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness...own verification strategy and execution from the block-level through full- chip (SoC) integration . + Sharp analytical and… more
    NVIDIA (11/13/25)
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  • Sr. Principal ASIC/Analog Design Engineer

    Teledyne (Goleta, CA)
    …our group is involved in early system trades as well as support for camera integration and production. You will be tasked take the lead in the design and analysis ... of the entire chip . This includes designing the circuitry of the signal...engineers on an image sensor are small, so each engineer is responsible for the design trades and implementation… more
    Teledyne (10/02/25)
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  • Senior Principal Emulation Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …impact on the world of technology. We are seeking a highly skilled Design Engineer to join our Palladium Solutions Development team, to drive the development of ... developing and integrating and validating high speed interface [Serdes, Chip 2 chip link] based subsystems in...circuits in analog Mixed Signal Designs and components (PHYs). Integration includes the PHY, Controller / Mac and the… more
    Cadence Design Systems, Inc. (11/18/25)
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  • Digital RF Systems Engineer , DBF Platform…

    Amazon (San Diego, CA)
    …refugee or granted asylum. Key job responsibilities As a Digital RF Systems Engineer working on the DBF Platform Software team you will be implementing, validating, ... develop RF impairment compensation and testing algorithms . Collaborate to drive chip and system specifications . Develop and optimize HW/SW calibration algorithms… more
    Amazon (10/18/25)
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  • RFIC Layout Design Engineer , Amazon Leo

    Amazon (San Diego, CA)
    …operating in locations without reliable connectivity. Role for Amazon Leo RFIC Layout design engineer : As a RFIC Layout design engineer , you will be an integral ... integral team with the RFIC/Mixed signal designers on full chip layout of custom analog and RFIC designs. Work...and LVS checks; and resolving errors. Proficiency top-level layout integration with ESD structures and pad assembly; Including density… more
    Amazon (11/19/25)
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  • Physical Verification Engineer (ASIC…

    ManpowerGroup (Phoenix, AZ)
    …**Tcl, Python, or Perl** scripting. + Validate **hierarchical verification flows** ( chip -level and block-level integration ). + Ensure compliance with ... **Job Title: Physical Verification Engineer (ASIC Design)** **Location: USA & Canada (Remote...ASIC designs. **Key Responsibilities** + Perform **physical verification** of full- chip and block-level layouts, including: + **DRC (Design Rule… more
    ManpowerGroup (11/14/25)
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  • Senior Design Verification and Methodology…

    Google (Sunnyvale, CA)
    Senior Design Verification and Methodology Engineer , Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving ... with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will...In this role, you will drive the efficiency of chip execution by creating and deploying design platforms. As… more
    Google (11/12/25)
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