- Qualcomm (San Diego, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (San Diego, CA)
- …teams (RTL, Physical Design , Circuits, CAD) to address critical physical design challenges in CPU implementations. + Develop innovative techniques ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU ...PPA Pathfinding Engineer, you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams… more
- Qualcomm (Santa Clara, CA)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and...nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical … more
- NVIDIA (Hillsboro, OR)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is seeking...fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks.… more
- Qualcomm (San Diego, CA)
- … operations for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + ... Engineer, you will lead innovative Central Processing Unit ( CPU ) design efforts that have a critical...Should have good exposure to high frequency design convergence for physical design … more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer, you will work with ... + Experience with Synthesis, place and route and signoff timing /power analysis. + Knowledge of high performance and low... design , Circuits, CAD) to solve key physical design problems in CPU … more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** We are hiring a talented...simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power… more
- Qualcomm (Santa Clara, CA)
- …synthesis, place & route and tape out flows. Roles and Responsibilities + Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP ... and physical design teams to design , floorplan and integrate the CPU designs...+ Proficiency in synthesis, place and route, and signoff timing /power analysis. + Expertise in block-level implementation as well… more
- Intel Corporation (Folsom, CA)
- …to meet power, performance, area, and timing goals as well as design integrity for physical implementation. + Reviews the verification plan and ... tomorrow. Who We Are We are working on the CPU design in Folsom. The team in...Finally, we have a backend integration working on full-chip timing , layout and design integration. Who You… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- NVIDIA (Santa Clara, CA)
- …skills and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out ... CPU , GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...(or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in… more
- Qualcomm (San Diego, CA)
- …and develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading ... the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define… more
- Amazon (Sunnyvale, CA)
- …device physics, custom/semi-custom implementation techniques - Experience solving physical design challenges across various technologies such as CPU , DDR, ... generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate...pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification,… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... + On-chip tightly coupled SRAM & L3 cache controller architecture/ design + Experience with x86 or ARM CPU...architecture/ design + Experience with x86 or ARM CPU /bus architectures + Ordering of memory transactions and methods… more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... a smarter, connected future for all. QCT Memory Controller Design Team is looking for ASIC Design ...interfaces to the rest of the system such as CPU , DSP, Multimedia Processors and the engineer is expected… more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... FPGA design flow (eg synthesis, timing closure, formality...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- Broadcom (San Jose, CA)
- …knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough knowledge of high-speed Ethernet networking and ... and working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with… more