- Qualcomm (San Diego, CA)
- … ASIC engineers with excellent analytical and technical skills, and a focus on low power , high performance ASIC designs, and, ability to execute critical ... low power designs. + Strong knowledge in the entire low power , high performance ASIC /SoC design flows (micro-architecture, RTL design, verification,… more
- The Boeing Company (Tukwila, WA)
- …Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for an ** ASIC and/or FPGA Design and Verification Engineer ** (Experienced, Lead or ... Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- The Boeing Company (Fairfax, VA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. And we're applying the latest...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- SpaceX (Irvine, CA)
- … power intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...flow, top-down and bottom-up design methodologies + Knowledge of low - power methodologies and leakage/dynamic power … more
- Qualcomm (San Diego, CA)
- …with mixed-signal IPs, such as SerDes, DDR, and Die-to-Die links - Experience in low - power digital design - Experience in creating tools and automation flows (in ... Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing...- Apply computer architecture and optimization techniques for improving power , performance, and area of the IPs - Assist… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 19. Experience with low power implementation, power gating,… more
- Meta (Columbus, OH)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 21. Experience with development of… more
- Meta (Sunnyvale, CA)
- …Memories. 22. Knowledge of STA signoff and understanding of AOCV, POCV 23. Experience with low power techniques for reducing power . 24. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Meta (Sunnyvale, CA)
- …Memories. 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with low power techniques for reducing power . 22. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Qualcomm (San Diego, CA)
- …designers at various levels to help with designing high-speed, high-performance and low - power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) ... applications. QCT mixed-signal design team consists of architects and ASIC designers, protocol experts, signal processing engineers, and algorithm designers… more
- NVIDIA (Santa Clara, CA)
- …Systems design. + Experience with multiple clock domains and asynchronous interfaces. + Experience in low power design and low power architecture. + ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of… more
- Amazon (Sunnyvale, CA)
- …implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design… more
- Amazon (Austin, TX)
- …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
- Broadcom (San Jose, CA)
- …Tcl scripting skill Other highly desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The ... challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from… more
- Qualcomm (San Diego, CA)
- …integrated circuit designers at various levels to help with designing high-performance and low - power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) ... design by course selections and/or work experience. + Experience working with ASIC design tools such as Cadence Virtuoso. **Preferred Qualifications** + Several… more
- Google (Mountain View, CA)
- …(IP) design for clocking, interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with ... logic synthesis techniques to improve RTL code, performance and power as well as low - power ...design techniques. + Experience with ARM-based SoCs, interconnects and ASIC methodology. + Experience with a scripting language like… more
- Amazon (Austin, TX)
- …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband… more
- Amazon (Austin, TX)
- …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Description Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low -latency, high-speed broadband… more
- NVIDIA (Westford, MA)
- …will be doing: + You will drive physical design and timing of high-frequency and low - power DPUs and SoCs at block level, cluster level, and/or full chip level. ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
- Google (Mountain View, CA)
- …years of industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies ... like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical… more