• Senior RTL Analysis Methodology

    NVIDIA (Santa Clara, CA)
    …can make a lasting impact on the world. We are looking for a motivated CAD Methodology Engineer to join our dynamic and growing team. If you like solving ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC and RDC...! We're responsible for the RTL CDC and RDC methodology for all of NVIDIA's semiconductor products. What you'll… more
    NVIDIA (02/14/25)
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  • Sr. Physical Design Methodology

    Amazon (Cupertino, CA)
    …integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, ... Accelerator chips in advanced nodes Drive improvement in RTL2GDS flows/ methodology for PPA and TAT improvements Create Dashboard and...in EE/CS - 5+ years in developing physical design methodology or CAD flows in synthesis, PNR, and sign-off… more
    Amazon (03/29/25)
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  • Senior Circuit Methodology Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Circuit Methodology Engineer ! Join NVIDIA's diverse team of innovators shaping the future of technology. From revolutionizing ... Engineering team, you will be contributing in the area of Circuit Methodology . Circuit simulator qualification and 3rd party (EDA) tool evaluation/integration will… more
    NVIDIA (03/16/25)
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  • SOC Verification and Methodology

    Qualcomm (San Diego, CA)
    …which are setting benchmarks in the whole industry. As an SOC Verification and Methodology Engineer , you will be responsible for ensuring the quality and ... tests to identify and resolve design issues. In this role of Design Verification Engineer , you will be using advanced state of the art tools, verification techniques… more
    Qualcomm (04/18/25)
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  • SOC Verification and Methodology

    Qualcomm (San Diego, CA)
    …which are setting benchmarks in the whole industry. As an SOC Verification and Methodology Engineer , you will be responsible for ensuring the quality and ... tests to identify and resolve design issues. In this role of Design Verification Engineer , you will be using advanced state of the art tools, verification techniques… more
    Qualcomm (02/12/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's ... for sign-off + Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics fundamentals of… more
    NVIDIA (04/18/25)
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  • DFX Methodology Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... I1500, I1687, IO BIST, memory BIST, scan and array dump and DFX security methodology . + In addition, you will help develop and deploy DFT methodologies for our… more
    NVIDIA (04/02/25)
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  • Senior CPU Implementation Methodology

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... stand out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting NVIDIA is widely… more
    NVIDIA (03/21/25)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of… more
    NVIDIA (03/13/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion Compiler to join our outstanding ... Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful,… more
    NVIDIA (03/11/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our outstanding Networking Silicon engineering ... team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional… more
    NVIDIA (03/11/25)
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  • Senior Methodology Software Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Methodology Software Engineer ! Join NVIDIA's diverse team of innovators shaping the future of technology. From revolutionizing ... Signal Design team, you will be contributing in the area of Software Methodology , designing and building software workflows to assist hardware design and debug. What… more
    NVIDIA (04/24/25)
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  • ASIC Methodology /CAD Engineer

    Amazon (Sunnyvale, CA)
    …Echo, and the Astro personal robot. What will you help us create? As an ASIC Methodology / CAD engineer you will create and maintain automated design flows that ... improve the efficiency and design quality of the finished ASIC products. Key job responsibilities - Develop automated flows for improving the SoC design process - Build robust, scalable tools that help verify and validate our hardware and software solutions -… more
    Amazon (03/12/25)
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  • ASIC Engineer , Methodology

    Meta (Austin, TX)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC vendor partners and ... **Summary:** Meta is hiring ASIC Methodology Engineers within our Infrastructure organization to work...Infrastructure organization to work on design integrity and signoff methodology development. We are looking for individuals with experience… more
    Meta (02/13/25)
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  • Physical Design Methodology Engineer

    Amazon (Austin, TX)
    …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to support physical design… more
    Amazon (03/04/25)
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  • ASIC Timing and Methodology Engineer

    Qualcomm (San Diego, CA)
    …Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing analysis targeting the ... and Tempus. + You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...contribution for STA timing sign off. + A timing Engineer should be able to understand all kind of… more
    Qualcomm (04/15/25)
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  • Physical Design/PDK methodology

    Applied Materials (Santa Clara, CA)
    …is a plus + Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) + ... Knowledge of standard cell architecture and design tradeoffs with respect to PPA + Proactively identify and act on new trends or developments in future technology nodes + Ability to implement solutions and troubleshoot complex problems with limited or no… more
    Applied Materials (03/25/25)
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  • Physical Design Methodology Engineer

    quadric.io, Inc (Burlingame, CA)
    …Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design methodologies and ... automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip tape outs as necessitated by… more
    quadric.io, Inc (03/11/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …closure + Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines ... What we need to see: + MS in Electrical or Computer Engineering (or equivalent experience) + Minimum 7 years' experience in Physical Design Engineering + Proven track record of PPA improvement on high performance and low power designs in advanced technology… more
    NVIDIA (02/20/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …gaming consoles and self driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams focus is on architecture and ... design of CMOS and Silicon-Photonics high-speed chip interfaces (NVLink, IEEE, PCIE, USB, OIF) and other complex photonic functions. Strong hands-on experience in the lab with silicon evaluation, debugging, characterization, and bring up. Do you want to work… more
    NVIDIA (04/19/25)
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