• Merck & Co. (Rahway, NJ)
    …patents, including development of sterile products for IV, IM, and/or SC route of administration (liquid and lyophilized).Experience, desire, and a track record of ... our company without a valid written search agreement in place for this position will be deemed the sole...an agency referral where no pre-existing agreement is in place . Where agency agreements are in place ,… more
    HireLifeScience (07/31/25)
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  • Merck & Co. (Durham, NC)
    …schedule.Must be willing to learn multiple CMMS system platforms and route engineering change requests through CMMS system.Expand knowledge into other systems, ... our company without a valid written search agreement in place for this position will be deemed the sole...an agency referral where no pre-existing agreement is in place . Where agency agreements are in place ,… more
    HireLifeScience (07/23/25)
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  • Sr. Staff CPU Physical Design CAD Engineer

    Qualcomm (Austin, TX)
    …+ Develop, integrate and release new features in our high-performance place -and- route CAD flow + Architect and recommend methodology improvements ... Engineering or Computer Science + Ten+ years of hands-on experience in place -and- route of high-performance chips - either in a design or CAD role… more
    Qualcomm (07/08/25)
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  • ASIC CAD Manager, Kuiper Silicon

    Amazon (Redmond, WA)
    place and route skills - RTL2GDS including floor planning synthesis place route clock construction - PPA Power Performance Area Optimization - Layout ... maintain standardized design flows and methodologies - Develop Synthesis and Place and Route methodologies in process nodes for external foundries - Enable the… more
    Amazon (07/31/25)
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  • CPU Server Floorplan and Integration Engineer

    Qualcomm (Santa Clara, CA)
    …using industry standard tools/flows. Ideal candidate should have + Proficiency in synthesis, place and route , and signoff timing/power analysis. + Expertise in ... is a plus + Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Roles and Responsibilities + Perform CPU physical design… more
    Qualcomm (07/23/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get ... Logical Equivalency Checking + Low Power Design Implementation, SDC Verification + Place and Route + Parasitic Extraction, Timing Signoff, Power Signoff + Be the… more
    Cadence Design Systems, Inc. (07/18/25)
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  • CPU Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …of library cells and optimizations. + Solid understanding industry standard tools for synthesis, place & route and tapeout flows. + Experience with Synthesis, ... level designs and perform optimizations. + Perform SynthPlace & Route on the designs using industry standard tools and...place and route and signoff timing/power analysis. + Knowledge of high… more
    Qualcomm (08/01/25)
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  • Senior Quantum Engineer - Cryo-CMOS Digital…

    Microsoft Corporation (Redmond, WA)
    …entry + RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, ... Verilog/System Verilog, design verification collaboration, CDC/Lint closure synthesis, floorplanning, place and route timing constraint, and post-silicon debug.… more
    Microsoft Corporation (08/01/25)
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  • SOC Physical Design Engineer, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …through synthesis, formal verification, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... design for synthesis, formal verification, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, IR… more
    Amazon (07/27/25)
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  • STA/Emir IC Solutions Architect

    Cadence Design Systems, Inc. (Austin, TX)
    …bug fixes. Work on various aspects of physical design including timing analysis, place and route , extraction, spice etc. Job Responsibilities: + Perform Static ... Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route , Clock Tree, RC Extraction, power and UPF/CPF concepts. + Execute… more
    Cadence Design Systems, Inc. (07/09/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Cupertino, CA)
    …physical implementation through synthesis, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... including synthesis, equivalency verification, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing… more
    Amazon (06/04/25)
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  • IC Physical Design Flow, Principal Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route , Design Closure, and timing/power signoff + Guide ... Design implementation process and steps + Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Physical Design Engineer - Multiple Levels

    Qualcomm (San Diego, CA)
    …role involves good understanding of functional and test (DFT) mode constraints for place and route , floorplanning, power planning, IR drop analysis, cell ... industry** **experience** **in the following areas:** - Physical Design - Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler -… more
    Qualcomm (07/12/25)
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  • Software Architect - FPGA Emulation/Prototyping…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Emulation/Prototyping guru + Experience working on delivery of EDA applications (synthesis/ place / route /timing/optimizations). + Expert in Timing & Clocking of ... is a plus + Working experience of EDA applications like synthesis/ place / route /timing/optimizations + Excellent programming skills in C/C++, Object Oriented… more
    Cadence Design Systems, Inc. (07/09/25)
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  • CPU Physical Design Pathfinding Engineer

    Qualcomm (San Diego, CA)
    …Power, Area and Performance goals. Must have skill/experience + Experience with Synthesis, place and route and signoff timing/power analysis. + Knowledge of high ... and optimizations. + Solid understanding of industry-standard tools for synthesis, place & route , and tapeout flows. + Strong data analytical skills to identify… more
    Qualcomm (07/03/25)
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  • Senior Applications Engineer (Aprisa)

    Siemens (Santa Clara, CA)
    …sales team to support the industry's rapidly expanding interest in Aprisa, the Siemens Place & Route offering. Since the acquisition of the technology, Siemens ... can be part of this growth.The JobSiemens EDA is looking for an experienced Place & Route user or Applications Engineer to play a critical role in our US-based… more
    Siemens (06/19/25)
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  • CPU Physical Design Methodology Engineer

    Qualcomm (Austin, TX)
    …Electrical Engineering with 5+ years of practical experience + Experience with Synthesis, place and route and signoff timing/power analysis. + Knowledge of high ... cells and optimizations. + Solid understanding industry standard tools for synthesis, place & route and tapeout flows. + Good data analytical skills to identify… more
    Qualcomm (05/20/25)
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  • Senior Physical Design Applications Engineer…

    Cadence Design Systems, Inc. (San Jose, CA)
    …teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: ... to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company… more
    Cadence Design Systems, Inc. (07/02/25)
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  • Senior Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …and low power SOC's. What you'll be doing: + Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions. + Integration on Analog ... experience. + 6+ years of hands-on experience in Physical design. + Place and route tool experience with Synopsys ICC2 or Candence Innovus + Static timing… more
    NVIDIA (07/24/25)
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  • Physical Design, Sr Principal AE

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route , Design Closure, and timing/power signoff + Guide customers ... experience with IC digital implementation flows and backend EDA tools including Place and Route , IR Drop, backend design timing and power closure + Experience… more
    Cadence Design Systems, Inc. (07/19/25)
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