• Senior Software Engineer, Place

    NVIDIA (Austin, TX)
    …(or equivalent experience) + 5+ years experience in one or more of these areas: place & route , spatial data structures, and design optimization. + Expertise in ... C++ + Thorough understanding of detailed placement, including incorporation of routing and timing algorithms. + Deep understanding of algorithm design principles such as complexity analysis, efficient memory and I/O use, etc. + Strong communication and… more
    NVIDIA (04/19/25)
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  • Memory System Designer and Place

    Broadcom (Mendota Heights, MN)
    …+ Architect and design memory subsystems + Implement RTL of subsystem designs + Place and route (physical design) + Design closure: timing, DRC, LVS, EM/IR, ... design skills + Ability to write and debug Verilog RTL code + Place and route expertise + Proficient in running STA, DRC, EM/IR tools, and attaining design… more
    Broadcom (02/25/25)
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  • Member of Technical Staff Physical Design - PnR…

    onsemi (Richardson, TX)
    …candidates a positive recruitment experience that builds our brand as a great place to work. **onsemi** is an Equal Opportunity and Affirmative Action employer. The ... Company maintains policies and practices that are designed to prevent discrimination or harassment against any qualified applicant or employee to the extent prohibited by federal, state and local laws and regulations. By way of example, discrimination on the… more
    onsemi (03/27/25)
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  • Sr. Staff CPU Physical Design CAD Engineer

    Qualcomm (Santa Clara, CA)
    …+ Develop, integrate and release new features in our high-performance place -and- route CAD flow + Architect and recommend methodology improvements ... Engineering or Computer Science + Ten+ years of hands-on experience in place -and- route of high-performance chips - either in a design or CAD role… more
    Qualcomm (03/06/25)
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  • Sr/Principal Engineer: FPGA/ASIC Engineer…

    Northrop Grumman (Gilbert, AZ)
    …analysis and systems architecture, design, coding, test bench design, verification, synthesis and place , & route for our Command and Data Handling (CD&H) ... in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route , static timing analysis, and power analysis + US Citizen + Must… more
    Northrop Grumman (05/02/25)
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  • ASIC CAD Manager, Kuiper Silicon

    Amazon (Redmond, WA)
    place and route skills - RTL2GDS including floor planning synthesis place route clock construction - PPA Power Performance Area Optimization - Layout ... maintain standardized design flows and methodologies - Develop Synthesis and Place and Route methodologies in process nodes for external foundries - Enable the… more
    Amazon (05/01/25)
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  • Product Engineer - FPGA Rtl Synthesis

    Siemens (Fremont, CA)
    …Synthesis solutions. College-level exposure to FPGA hardware design through RTL Synthesis and Place & Route is key. AMD/Xilinx or Intel/Altera, Lattice, or ... + Analyze and rework RTL FPGA designs to improve end results in Place & Route + Create and deliver customer training on FPGA Synthesis and associated… more
    Siemens (04/18/25)
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  • CPU Physical Design Engineer

    Qualcomm (San Diego, CA)
    …of library cells and optimizations. + Solid understanding industry standard tools for synthesis, place & route and tapeout flows. + Experience with Synthesis, ... level designs and perform optimizations. + Perform SynthPlace & Route on the designs using industry standard tools and...place and route and signoff timing/power analysis. + Knowledge of high… more
    Qualcomm (04/01/25)
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  • Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …physical implementation through synthesis, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... including synthesis, equivalency verification, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing… more
    Amazon (03/19/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …physical implementation through synthesis, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... including synthesis, equivalency verification, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing… more
    Amazon (03/04/25)
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  • Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …role involves good understanding of functional and test (DFT) mode constraints for place and route , floorplanning, power planning, IR drop analysis, cell ... industry** **experience** **in the following areas:** - Physical Design - Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler -… more
    Qualcomm (04/28/25)
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  • Product Engineer II

    Cadence Design Systems, Inc. (San Jose, CA)
    …Seeking a highly motivated engineer who can drive improvement to Cadence's synthesis and place & route products from a design perspective. The position provides ... synthesis space with the goal to bridge the gap between logic synthesis and place and route + Support the field engineers in Cadence Design Systems, Inc. and its… more
    Cadence Design Systems, Inc. (04/23/25)
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  • CAD Engineer

    Cisco (San Jose, CA)
    …Impact: As a CAD Support Engineer, you will provide expert-level support for Synthesis and Place & Route tools and related EDA flows. You will partner closely ... in CAD support, ASIC design, or related roles with a focus on Place & Route tools. * Strong expertise in Innovus, Fusion Compiler, and other P&R tools.… more
    Cisco (04/22/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route , clock tree synthesis, static timing ... Primetime, Redhawk/Voltus, or Calibre. 14. Experience in floor planning, place & route , power and clock distribution, and timing convergence of high-frequency… more
    Meta (04/22/25)
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  • Software Architect - FPGA Emulation/Prototyping…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Emulation/Prototyping guru + Experience working on delivery of EDA applications (synthesis/ place / route /timing/optimizations). + Expert in Timing & Clocking of ... is a plus + Working experience of EDA applications like synthesis/ place / route /timing/optimizations + Excellent programming skills in C/C++, Object Oriented… more
    Cadence Design Systems, Inc. (04/09/25)
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  • CPU Physical Design Pathfinding Engineer

    Qualcomm (San Diego, CA)
    …Power, Area and Performance goals. Must have skill/experience + Experience with Synthesis, place and route and signoff timing/power analysis. + Knowledge of high ... and optimizations. + Solid understanding of industry-standard tools for synthesis, place & route , and tapeout flows. + Strong data analytical skills to identify… more
    Qualcomm (04/03/25)
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  • Senior Physical Design Applications Engineer…

    Cadence Design Systems, Inc. (San Jose, CA)
    …teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: ... to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company… more
    Cadence Design Systems, Inc. (04/02/25)
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  • Backend Digital Design Sr Principal Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route , Design Closure, and timing/power signoff + Guide customers ... experience with IC digital implementation flows and backend EDA tools including Place and Route , IR Drop, backend design timing and power closure + Experience… more
    Cadence Design Systems, Inc. (05/01/25)
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  • Fpga Engineer

    Actalent (Fargo, ND)
    …FPGA. + Generate and synthesize Verilog/VHDL code. + Develop and implement FPGA constraints, place and route , and perform timing analysis. + Adapt digital design ... generation and synthesis. + Ability to develop and implement FPGA constraints, place and route , and timing analysis. + Ability to adapt digital design to vehicle… more
    Actalent (04/24/25)
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  • R&D Engineer IC Design

    Broadcom (San Jose, CA)
    …circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route , and timing and power use. Analyzes equipment to ... 12+ years experience, or MS with 10+ years experience. Must have strong Place and Route back ground and drive timing closure using Innovus, ICC2 in 16nm… more
    Broadcom (04/15/25)
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