- Qualcomm (San Diego, CA)
- …Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful ... candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC,...blocks of Hexagon DSP core and sub-system + Develop RTL for multiple logic blocks of Hexagon DSP core… more
- Qualcomm (Austin, TX)
- …Group > CPU Engineering **General Summary:** We are hiring talented engineers for CPU RTL Power targeted for high performance, low power devices. In this role, you ... key aspects of CPU power modeling and analysis, and RTL power estimation and optimization of high-performance energy efficient...Computer Engineering with 3 - 8 years of CPU RTL power modeling and estimation experience. * Deep understanding… more
- Qualcomm (Austin, TX)
- …this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and ... RTL Design Engineer, you will work with chip architects...architectural research and arriving at a detailed specification. + RTL ownership. Development, assessment and refinement of RTL… more
- Qualcomm (Santa Clara, CA)
- …> CPU Engineering **General Summary:** We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you ... principles along with timing and power implications. **Roles and Responsibilities** As an RTL engineer you will own or participate in the following: * Performance… more
- NVIDIA (Santa Clara, CA)
- …see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and ... supports static RTL verification methodologies for RTL Lint and Logical Equivalence. As part of the VLSI organization, our team defines advanced methodologies… more
- Qualcomm (Boxborough, MA)
- …in all its businesses. We are looking for a hardware micro-architects and RTL designers to develop Adreno GPU for Qualcomm Snapdragon compute platforms across the ... and automotive solutions. **What you will be doing** : Micro-architect and design RTL for blocks and modules of Adreno GPU architecture across shader processing,… more
- Cadence Design Systems, Inc. (Austin, TX)
- …of technology. Cadence Solutions (North America) team is looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs ... work with verification/validation team to create performance verification plan + RTL development + Support Verification teams. Support test bench development, review… more
- IBM (Austin, TX)
- …innovation thrive. Your Role and Responsibilities As a CPU Core Microarchitect and RTL Designer you will be responsible for defining and implementing the logical ... architecture, and software. + Own and deliver the detailed RTL implementation of specific CPU Core IP. + Refine...Expertise + 5+ years of experience architecting and/or delivering RTL + Demonstrated expertise in architecting and designing specific… more
- Cadence Design Systems, Inc. (Austin, TX)
- …includes the following operations and requirements: + Work on projects to deploy Cadence RTL - GDSII tool adoption in Synthesis with Genus, Place & Route with ... tapeouts and benchmarks + Areas of Technology exposure include: + RTL Synthesis/Physical Synthesis, Design constraint creation , Floorplanning, Power Grid Synthesis,… more
- NVIDIA (Santa Clara, CA)
- …infrastructure tools used by design engineers for build and verification of architectural, rtl , and gate level designs. As a software engineer, you will craft highly ... Develop and enhance C++ based software tools to improve RTL design productivity and quality + Research and develop...stand out from the crowd: + Good architecture and RTL design knowledge + Strong expertise in modern C++,… more
- Cadence Design Systems, Inc. (Austin, TX)
- …and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII. Lead technical campaigns and strategies in the RTL ... Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII. Experience in scripting in Perl/Tcl/Python to automate and implement… more
- Google (Mountain View, CA)
- …experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Preferred ... . + Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU. + Propose performance enhancing… more
- Cadence Design Systems, Inc. (Austin, TX)
- …top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in ... Mobile Customers * Senior level Application Engineer position supporting RTL -to-GDS implementation flows using Encounter Digitial Implementation Platform * Manage… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Synthesis, DFT, and Logical Equivalence Checking, Low Power, Power characterization. Expert in RTL Synthesis and ability to rewrite RTL to accomplish improved ... PPA. Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must. Experience with advanced technology nodes including Sub 5nm and below. Develop, debug, and optimize various aspects of design flows for SoC's to achieve… more
- BAE Systems (Manchester, NH)
- …on position level and/or job specifics. **Hardware Engineering Manager - RTL Design Verification (Hybrid)** **98875BR** EEO Career Site Equal Opportunity Employer. ... Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression more
- Cadence Design Systems, Inc. (San Jose, CA)
- …is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + IP integration and verification ... + Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus. + Understanding of digital architecture trade-offs for power, performance, and area + Understanding of proper handling of multiple asynchronous clock domains and their crossings +… more
- Cadence Design Systems, Inc. (Austin, TX)
- …with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow. You have proven hands-on experience with timing closure and PPA ... optimization at 16nm and below nodes. You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach. You are an excellent communicator. The annual salary range for… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and ... timing/power signoffGuide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedulesConduct technical presentations and product demonstrationsDrive technical evaluations/benchmarks to successWork closely with… more
- Qualcomm (Santa Clara, CA)
- …* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, ... Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering,… more
- Microsoft Corporation (Mountain View, CA)
- …will be responsible for developing and maintaining the Register Transfer Level ( RTL ) design flows and methodologies for our cutting edge chip productions. Throughout ... for testing( DFT) and physical design to ensure quality, performance and efficiency of RTL code and tools. Microsoft's mission is to empower every person and every… more
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