- Cisco Systems, Inc. (San Jose, CA)
- …experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, ... post silicon validation phases with additional exposure to physical design signoff activities. Key Contributions: Manages the definition, architecture and design of… more
- Cisco Systems, Inc. (San Jose, CA)
- …functional verification DFT CAD development - Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT ... post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware… more
- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- SpaceX (Bastrop, TX)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer,...signoff ownership, constraint authoring and verification, full chip static timing analysis and ... 5 years of experience in static timing (ie, full chip timing ...successful timing closure. + Participate in both static timing analysis methodology development… more
- Google (Sunnyvale, CA)
- Staff Static Timing Analysis Lead,...development and support, as well as chip implementation and timing signoff execution. + Develop, support and ... field or equivalent practical experience. + 8 years of experience with Static Timing Analysis (STA) activities, including project planning, scheduling, task… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... and customer sites. Requirements; 8+ years of experience in Static timing analysis , Individual should...Tempus - Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure… more
- Broadcom (San Jose, CA)
- …Develop and validate timing constraints for intricate SoC designs. + Perform static timing analysis (STA) using industry-standard tools (eg, PrimeTime, ... Tempus). + Define and implement timing signoff methodologies, including process corners, derates,... timing checks and quality of results (QoR) analysis . + Automate timing analysis … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design ... SDC Verification + Place and Route + Parasitic Extraction, Timing Signoff , Power Signoff +...Synopsys place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis ) + Debug… more
- Cisco (San Jose, CA)
- …experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, ... post silicon validation phases with additional exposure to physical design signoff activities. **Key Contributions:** + Manages the definition, architecture and… more
- SpaceX (Sunnyvale, CA)
- … budgeting and constraint pushdown to partition owners + Work with static timing analysis , physical verification, electromigration/voltage drop, noise ... and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout +… more
Locations:
California,
Texas