• Sr. SOC /ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
    SpaceX (04/15/25)
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  • Sr. SOC /ASIC Physical Design

    SpaceX (Bastrop, TX)
    Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
    SpaceX (04/15/25)
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  • SoC Physical Design

    Google (Mountain View, CA)
    …or a related field, or equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools (eg, Genus, ... + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design Implementation including UPF/CPF,… more
    Google (03/29/25)
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  • Staff Engineer - HBM SOC

    Micron Technology, Inc. (Richardson, TX)
    …the industry! **Position Overview:** Micron is hiring a Staff Engineer - HBM SOC Physical Design ! You will be responsible for the design & ... + Resolving and improving design and flow issues related to physical design , identifying potential solutions, and working with CAD teams as needed. +… more
    Micron Technology, Inc. (04/29/25)
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  • SoC Power Design Engineer

    Qualcomm (San Diego, CA)
    …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...**Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of… more
    Qualcomm (02/13/25)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (Seattle, WA)
    **Job Role:** ** SOC Design Verification Engineer ** **Job location: Seattle WA** **Job Description:** We are looking for SOC Design Verification ... digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - SOC Design Verification… more
    Capgemini (04/15/25)
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  • Principal Engineer - HBM SOC

    Micron Technology, Inc. (Richardson, TX)
    …the lowest power per bit solutions in the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design ... partners to ensure the success of our HBM roadmap. Your deep understanding of SOC Architecture, RTL Logic Design , IP Integration, high-speed interface design more
    Micron Technology, Inc. (03/21/25)
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  • SoC RTL Security Design

    Google (Sunnyvale, CA)
    …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team working ... on SoC -level RTL design for our data center accelerators. You will ...and debug design RTL. + Work with physical design teams to ensure design...design RTL. + Work with physical design teams to ensure design meets … more
    Google (04/26/25)
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  • SOC /ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …weekends to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/Timing Engineer /Level I: $120,000.00 - $145,000.00/per ... SOC /ASIC Timing Signoff & Front-End Implementation Engineer ...year Physical Design STA/Timing Engineer /Level II: $140,000.00 - $170,000.00/per year… more
    SpaceX (04/15/25)
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  • Sr. SOC /ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
    SpaceX (04/15/25)
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  • Embedded Software Engineer - Senior…

    Capgemini (MN)
    **Job description:** We are looking for a Senior Hardware SoC Model Engineer with expertise in Renode. The ideal candidate will have a strong background in ... **Job:** _Programmer/Analyst_ **Organization:** _ERD PPL US_ **Title:** _Embedded Software Engineer - Senior Hardware SoC Model Engineer_ **Location:**… more
    Capgemini (03/11/25)
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  • Sr. Systems Engineer SOC

    AutoZone, Inc. (Memphis, TN)
    …This may include, but not limited to: Responsible for technical design and administration of security controls, services, and architecture, eg infrastructure ... skills Advanced problem solving, domain technical and analytical skills Advanced system design and implementation skills Advanced knowledge of more than one of the… more
    AutoZone, Inc. (03/27/25)
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  • SOC / SIRT Engineer

    Datavant (Columbus, OH)
    …We're Looking For** Become a vital defender of our digital landscape as a SOC /SIRT engineer . You'll monitor and analyze security alerts, swiftly respond to ... effective coordination and communication across technical teams and stakeholders. + Design , mature, and implement advanced playbooks for triage, investigation, and… more
    Datavant (03/27/25)
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  • ASIC Engineer , Physical

    Meta (Sunnyvale, CA)
    …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... Knowledge of geometry/process/device technology implications on physical design . 16. Experience with large SOC designs...physical design . 16. Experience with large SOC designs (>20M gates) with frequencies over 1GHZ. 17.… more
    Meta (04/22/25)
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  • Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    … engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using ... technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU,… more
    Qualcomm (04/28/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks +… more
    SpaceX (04/15/25)
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  • Senior FPGA Design Engineer (Space…

    Umbra Lab (Santa Barbara, CA)
    …that has never meaningfully existed before. We are seeking a Senior FPGA Design Engineer (Space Systems), developing HDL based digital designs supporting ... identity, sexual orientation, race, color, religious creed, national origin, physical or mental disability, protected veteran status, or any...+ 7+ years of proven, relevant experience in digital design with FPGA and SoC devices. +… more
    Umbra Lab (04/23/25)
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  • CPU Physical Design Pathfinding…

    Qualcomm (San Diego, CA)
    …a CPU PPA Pathfinding Engineer , you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams to lead the cutting-edge ... + Strong data analytical skills to identify and address physical design issues. + Experience in pre-post...methods relevant to the designs. + Partner with Process, SoC and Post-silicon teams to analyze, improve design more
    Qualcomm (04/03/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …Experience in SoC bus and interconnect protocols 12. Knowledge of physical design and low-power implementation 13. Experience with high-speed I/O protocols ... power machine learning accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital… more
    Meta (04/18/25)
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  • Physical Design Lead Engineer

    Cisco (San Jose, CA)
    …foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams. * Experience working with Package and ... for verification robustness. * Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend,… more
    Cisco (04/02/25)
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