- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 12 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- NVIDIA (Westford, MA)
- … tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon...be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at… more
- NVIDIA (Santa Clara, CA)
- …with 2+ years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level,… more
- NVIDIA (Santa Clara, CA)
- …+ Experience with coding- TCL, Python. Must have hands-on experience with NanoTime static timing analysis , its algorithms and associated circuit constraint ... custom circuit design using NanoTime and various spice simulations. + The timing analysis will include the application of variation and statistical parameters in… more
- NVIDIA (Santa Clara, CA)
- …PT. + Expertise in coding- TCL, Python. Must have hands-on experience with NanoTime static timing analysis , its algorithms and associated circuit constraint ... custom circuit design using NanoTime and various spice simulations. + The timing analysis will include the application of variation and statistical parameters in… more
- NVIDIA (Santa Clara, CA)
- …design and/or timing closure experience with successful tapeouts. + Expertise in Static Timing Analysis and prior working experience with STA tools ... of AI chips. What you will be doing: + Drive robust methodology for timing analysis of custom circuit IP. + Support SRAM and other custom circuit design… more
- Qualcomm (San Diego, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Cadence Design Systems, Inc. (Austin, TX)
- … analysis , place and route, extraction, spice etc. Job Responsibilities: . Perform Static timing analysis , glitch, noise analysis , extraction using ... related field of VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows,… more
- Siemens Digital Industries Software (Wilsonville, OR)
- …circuit design, and design implementation flows with particular emphasis on delay constraints, static timing analysis , and timing optimization ... other related fields. + Minimum of 5 year's experience of design, static timing analysis , and Tcl/Python scripting + Software Engineering skills, especially… more
- ManpowerGroup (Phoenix, AZ)
- …low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis , formal verification, Gate level ... achieving optimal synthesis QoR on low power designs + Knowledge of static timing analysis , defining timing constraints and exceptions, corners/voltage… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …includes RTL integration, maintain the timing constraint, Synthesis, Place and Route, Static timing analysis (STA), timing closure, power ... will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon bring up with the validation… more
- Cisco (Maynard, MA)
- …placement, CTS, routing) * Power, performance and area optimization of design * Static Timing analysis and signoff closure * Physical verification ... week * Knowledge of the design cycle from RTL to GDSII * Understanding of Static Timing Analysis , timing closure and design constraints * Knowledge in… more
- Cadence Design Systems, Inc. (Austin, TX)
- …identify potential solutions and drive execution. + Run, debug, and fix signoff closure issues in static timing analysis (STA). + Full chip & block level ... design skills as well as physical design skills for timing closure. + Closely collaborate with the ASIC design...ASIC design team to drive architectural feasibility studies, develop timing , power and area design targets, and explore RTL/design… more
- Microsoft Corporation (Redmond, WA)
- …of experience with Verilog/System Verilog coding constructs. + 3+ years of experience in Static Timing Analysis and timing signoff fundamentals. **Other ... create, and maintain project documentation, including design documents with analysis reports. + Develop micro-architectural understanding of mixed-signal systems on… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Equivalence Checking Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Good hands-on ... experience of Floorplanning , Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite Advanced clock tree synthesis techniques including… more
- NVIDIA (Santa Clara, CA)
- …power/clock distribution, chip assembly and P&R, timing closure. + Craft designs for static timing analysis , power and noise analysis and back-end ... Initiatives is a plus. + Already a validated strong power user of P&R, Timing analysis , Physical Verification and IR Drop Analysis CAD tools from Synopsys… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis , computer architecture, verification, RTL ... large software development projects is highly recommended + Prior experience with timing analysis software development projects is highly recommended The annual… more
- Siemens Digital Industries Software (Wilsonville, OR)
- …products, comprising of high-level synthesis, FPGA and logic synthesis, place & route, static timing analysis , end-to-end power optimization and analysis ... experience in synthesis, test, place and route, power analysis , and static timing analysis , is a plus. + Experience developing commercial and innovation… more
- Cisco (San Diego, CA)
- …experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure, ... team will participate in the creation of Innovative Hardware DFT & Test timing analysis for new silicon device models, bare die & stacked die, driving re-usable… more
- SpaceX (Sunnyvale, CA)
- …solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more