- Actalent (Dallas, TX)
- FPGA UVM Verification Engineer Job Description We are seeking a skilled FPGA UVM Verification Engineer with a strong experience in networking to ... join our innovative team. The FPGA Verification Engineer will be responsible for developing...on networking applications. This role requires expertise in Universal Verification Methodology ( UVM ) and a solid understanding… more
- US Tech Solutions (Goleta, CA)
- …AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer , you will own functional ... and testing. **Mandatory:** + 8 years of experience with verification methodologies and languages such as UVM ...with verification methodologies and languages such as UVM and SystemVerilog. + Experience developing and maintaining … more
- US Tech Solutions (Goleta, CA)
- …and GLS bringup and testing **Experience:** + 6+ years of experience with verification methodologies and languages such as UVM and SystemVerilog. + Experience ... Experience in analog and real number modeling preferred **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG + SDF and GLS… more
- Amazon (Redmond, WA)
- …networking and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating & Maintaining ...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA based… more
- Skyworks (Cedar Rapids, IA)
- Sr. Verification Engineer Apply now " Date:May...expected and verify model accuracy + Write System Verilog UVM testbench code for die level verification ... ID: 75221 Description If you are a Mixed Signal Verification engineer with 4+ years of experience,... UVM libraries + 2+ years experience writing UVM testbenches for mixed signal verification +… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
- Actalent (Redmond, WA)
- Job Title: Silicon Verification Engineer Job Description The Silicon Verification Engineer plays a crucial role in the test-plan generation process, ... field of AI technology. Responsibilities + Define, document, and implement a UVM verification environment, including agents and scoreboards. + Write test… more
- Northrop Grumman (Linthicum Heights, MD)
- …career. We are looking for you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification Engineer based out of ... This requisition may be filled as a Principal Digital Engineer or a Senior Principal Digital Engineer ....complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. +… more
- SpaceX (Redmond, WA)
- Design Verification Engineer (Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
- ManpowerGroup (Redmond, WA)
- Our client, a leader in technology innovation, is seeking a Silicon Verification Engineer 2 to join their team. As a Silicon Verification Engineer 2, you ... mindset which will align successfully in the organization. **Job Title:** Silicon Verification Engineer 2 **Location: Redmond, WA (Remote)** **Pay Range:**… more
- Northrop Grumman (Annapolis Junction, MD)
- …level. Qualifications for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a technical area ... security clearance with Polygraph** **.** **Basic Qualifications Senior Principal Digital Verification Engineer :** + Bachelor's degree in a technical area… more
- ManpowerGroup (Austin, TX)
- Our client, a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As a Silicon Verification Engineer , you ... mindset which will align successfully in the organization. **Job Title:** Silicon Verification Engineer **Location:** Austin, TX **What's the Job?** + Focus… more
- Meta (Sunnyvale, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology. 9. 3+ years… more
- Meta (San Diego, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a ... cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog- UVM , coverage development, assertion model… more
- Amazon (Sunnyvale, CA)
- Description As a Design Verification (DV) Engineer , you will be part of an advanced architecture team that is exploring new hardware designs to improve our ... working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM - Identify and write… more
- Amazon (Boise, ID)
- …Fire TV and Amazon Echo. What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will be part of an advanced engineering and research ... by working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. -… more
- BAE Systems (Westminster, CO)
- …be available based on position level and/or job specifics. **Principal FPGA Verification Engineer ** **110108BR** EEO Career Site Equal Opportunity Employer. ... test benches for both unit level and system level environments, and create reusable verification environments that can be used across multiple projects. + Work in a… more