• Firmware/ FPGA Design

    Leidos (San Diego, CA)
    …is part of the Leidos National Security Sector engineering space development team. As a **Firmware/ FPGA Design Engineer ** in Leidos, you will be an integral ... solutions for various cutting edge hardware platforms, boards, and FPGAs. The FPGA /Firmware design engineer will work with a multi-disciplined design more
    Leidos (05/24/24)
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  • Firmware/ FPGA Design

    Leidos (San Diego, CA)
    …is part of the Leidos National Security Sector engineering space development team. As a **Firmware/ FPGA Design Engineer ** in Leidos, you will be an integral ... solutions for various cutting edge hardware platforms, boards, and FPGAs. The FPGA /Firmware design engineer will work with a multi-disciplined design more
    Leidos (05/18/24)
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  • Sr. FPGA /ASIC Design

    SpaceX (Sunnyvale, CA)
    …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC/ FPGA Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. FPGA /ASIC Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring… more
    SpaceX (05/17/24)
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  • Principal or Senior Principal Digital…

    Northrop Grumman (San Diego, CA)
    …of history, they're making history. Explore a career engineering what's possible as a Digital Design Engineer in San Diego, CA. **What You'll Get to Do:** Our ... the beach Southern California is famous. As a Digital Design Engineer at Northrop Grumman, you will...0 years with PhD. + Must have hands on FPGA design experience with VHDL within the… more
    Northrop Grumman (06/04/24)
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  • Senior Principal Firmware Design

    RTX Corporation (Goleta, CA)
    …that create a safer, more secure world. The Senior Principal Firmware Design Engineer is responsible for requirements analysis and decomposition, sub-system ... design verification test. The Sr Principal FW Design Engineer will work with other experienced... in the following areas: + Subsystem/Module Digital Circuits, FPGA knowledge, COTS Interfaces, High Speed Memory Interfaces, Subsystem… more
    RTX Corporation (04/04/24)
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  • Sr. ASIC Design Engineer , DDR IP…

    SpaceX (Sunnyvale, CA)
    …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/ FPGA Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer , DDR IP (Silicon Engineering)...Sr. ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Sunnyvale,...goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER , DDR IP (SILICON ENGINEERING) At… more
    SpaceX (03/29/24)
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  • Lead, FPGA Design Engineer

    L3Harris (San Diego, CA)
    Job Title: Lead, FPGA Design Engineer - Technical Lead (Secret Clearance) Job Code: 11653 Job Location: San Diego, CA Job Description: This self-motivated ... space and airborne domains with defense, intelligence, and commercial applications. As an FPGA design engineer , you will be directly involved in the … more
    L3Harris (06/06/24)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …next chapter of your career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** to join our Engineering Group, reporting to both ... of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
    Silvus Technologies (05/21/24)
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  • FPGA DSP Firmware Design

    Leidos (San Diego, CA)
    …The Electronic Warfare Division of the Leidos Innovation Center is looking for a FPGA DSP Firmware Design Engineer to work with a multi-disciplined ... team (electrical engineers, systems engineers, scientists, etc) to design , develop, simulate, and integrate challenging DSP FPGA... design , develop, simulate, and integrate challenging DSP FPGA designs and RF sensor systems based on given… more
    Leidos (05/16/24)
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  • Staff Digital Design Engineer

    Northrop Grumman (San Diego, CA)
    …of history, they're making history. Explore a career engineering what's possible as a Digital Design Engineer in San Diego, CA. **What You'll Get to Do:** Our ... beach Southern California is famous. As an Electrical/ Digital Design Engineer at Northrop Grumman, you will...and define possible? If you have hands-on experience in FPGA Development with VHDL, apply today. Roles and Responsibilities:… more
    Northrop Grumman (06/04/24)
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  • Senior Principal Front End ASIC Design

    BAE Systems (San Jose, CA)
    …on position level and/or job specifics. **Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO Career Site Equal Opportunity Employer. ... or Computer Science + Proficient in Verilog language for Front End ASIC design , and related FPGA + Knowledge of ASIC design flows is highly desirable, and… more
    BAE Systems (06/07/24)
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  • Senior Microelectronics Design

    Leidos (San Diego, CA)
    **Description** The EW Division of Leidos is looking for a part-time Senior Microelectronics Design Engineer to work with a multi-disciplined design team ... etc.) * Lead a microelectonics design team to design , integrate and test challenging DSP FPGA designs for EW sensor systems. * This position will interface… more
    Leidos (05/18/24)
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  • Hardware Design Engineer

    Leidos (San Diego, CA)
    …Innovations Center (LInC) at Leidos currently has an opening for a mid-level hardware design engineer to support a portfolio of programs in San Diego developing ... Qualifications: + Masters' degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/ FPGA design is a plus. + 2+ years of ASIC and/or… more
    Leidos (05/07/24)
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  • Microelectronics ASIC Design

    Leidos (San Diego, CA)
    **Description** The EW Division of Leidos is looking for a Microelectronics Design Engineer to work with a multi-disciplined design team (electrical ... engineers, systems engineers, scientists, etc) to design , develop, simulate, and integrate innovative custom microelectronics in support of warfighter missions.… more
    Leidos (05/01/24)
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  • Sr. Design Verification Engineer

    SpaceX (Irvine, CA)
    Sr. Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SR. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block and system level + Write… more
    SpaceX (06/06/24)
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  • Senior Design Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Design Verification Engineer ! What you'll be doing: + Technical leadership role to define/plan/implement/execute verification ... strategy of complex design . + Ability to delve into lowest level details.../ VC Formal) is a plus. + Experience with gate -level simulation, reset verification, contention checking is a plus.… more
    NVIDIA (05/25/24)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …custom Intellectual Property (IP) components. + Define pre-Silicon verification (simulation/emulation/formal proofs/ field-programmable gate array ( FPGA ) ... clients, and augmented reality. We are looking for a **Senior Design Verification Engineer ** to work on leading-edge Intellectual Property (IP) development as… more
    Microsoft Corporation (05/24/24)
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  • SOC Design Engineer

    Google (Sunnyvale, CA)
    design methodologies for clock domain checks, reset checks and low power design . + Experience with silicon, emulation, FPGA validation and debug, functional ... and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's… more
    Google (04/24/24)
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  • Senior Applications Engineer , DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …. Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design . Knowledge of AXI, DFI protocols . Working knowledge of memory ... to make an impact on the world of technology. Title Senior Applications Engineer - DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team… more
    Cadence Design Systems, Inc. (04/03/24)
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  • Hardware Design Engineer - Staff

    Qualcomm (San Diego, CA)
    …to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design , optimize, verify, and test electronic systems, ... mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA , and/or DSP systems that launch cutting-edge, world class… more
    Qualcomm (05/01/24)
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