- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals with ... be a hands-on domain professional, able to traverse from RTL to final design closure (timing and layout) involving...scripting languages + Hands-on experience with physical design and analysis tools from EDA vendors such as Cadence, Synopsys,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and CAD teams to ... experience + Experience with Synthesis, place and route and signoff timing/power analysis . + Knowledge of high performance and low power implementation techniques +… more
- Meta (Sunnyvale, CA)
- …with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System ... Perform RTL Lint and work with the Designers to create waivers. 5. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 6. Perform Flat… more
- SpaceX (Irvine, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX...teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +… more
- NVIDIA (Santa Clara, CA)
- …GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You ... are now looking for a Power Architecture and Optimization Engineer - New College Grad! NVIDIA prides in having...internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve… more
- Qualcomm (San Diego, CA)
- …help create a smarter, connected future for all. As a Qualcomm GPU Engineer , you may architect, design, implement, verify, and/or optimize the performance and power ... or related field. **Job Description:** + Synthesize the Verilog RTL and create models and compile them to emulators...emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance. + Drive debug failures… more
- Northrop Grumman (Linthicum, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug **Senior Principal Engineer Basic Qualifications:** + Bachelor's ... to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification Engineer based out...techniques. + Perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level… more
- Micron Technology, Inc. (Atlanta, GA)
- …flow and DFT verification. + Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis . + Familiarity with ... to enrich life. Micron is searching for its next Principal/Senior Design Verification Engineer ! In this role, you will work with a highly innovative and motivated… more
- NVIDIA (Santa Clara, CA)
- …Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis , methodology alignment, and program execution to ensure pre-silicon and ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation...of external and internal IPs. + Contribute to cross-team RTL methodologies to achieve efficient design reuse. + Evaluate… more
- Microsoft Corporation (Redmond, WA)
- …for a **Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** to work as digital Application Specific Integrated Circuit (ASIC) ... are looking for **Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** who is as passionate about their own contribution as they… more
- Qualcomm (Santa Clara, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop ... STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to… more
- Northrop Grumman (Linthicum, MD)
- …cyberspace. NGMS, Digital Technologies Group, is seeking a Staff Digital Verification Engineer to support ASIC and FPGA product development. In this capacity, you ... individual will perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level...block level and SOC level using UVM (Universal Verification Methodology ) and SystemVerilog. This task includes but not limited… more
- Meta (Sunnyvale, CA)
- …in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power Analysis and Optimization 19. Experience ... and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3.… more
- Siemens Digital Industries Software (Wilsonville, OR)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... planning, physical design/verification, muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …(TCL and Perl) Proficiency with synthesis, logic equivalence, DFT and backend related methodology and tools Strong background in Constraint analysis and debug, ... span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the timing constraint, Synthesis, Place and Route, Static timing… more
- BAE Systems (San Jose, CA)
- …strong proficiency in both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench ... creation, functional coverage, test failures analysis , regression Detail requirements + Front..., regression Detail requirements + Front End Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from… more
- NVIDIA (Santa Clara, CA)
- …reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design ... We are now looking for an Architecture Energy Modeling Engineer ! At NVIDIA, we pride ourselves in having energy-efficient products. We believe that continuing to… more
- NVIDIA (Santa Clara, CA)
- …verification methodology + Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis + Excellent ... for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design, synthesis, timing + Silicon bring-up + SOC level integration… more
- ManpowerGroup (Phoenix, AZ)
- **Job Title:** **Physical Design-Power Integrity Flow Development Engineer ** **Location:** + **Primary:** Phoenix, AZ + **Secondary:** Remote in the US. **Experience ... or GC preferred. **Job Description:** + Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC...of ASIC SoC design at various design stages, from RTL to gate-level netlist. + Develop and own power… more