- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role ... in improving the netlist and timing quality of our designs and if you are...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs, GPUs, SoCs at...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. + Finding the right tradeoffs… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. What you'll be doing: + Drive DFT/Test timing for innovative GPUs, CPUs, and SoCs at cluster level and/or full chip ... level + Work on all aspects of DFT/Test timing such as timing constraints, timing...and clock controls in DFT modes + Experience in methodology or flow development + Great problem-solving skills, self-motivated… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- NVIDIA (Santa Clara, CA)
- …looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus on improving the PPA… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...for high coverage on silicon - Review sign-off level timing closure using static timing analysis of… more
- Cadence Design Systems, Inc. (Austin, TX)
- …who want to make an impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to ... should include ASIC design using industry-standard hardware description languages (Verilog) * Senior Level Applications Engineer position with Deep Cadence or… more
- BAE Systems (San Jose, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench… more
- Teradyne (Tualatin, OR)
- …team working in an exciting, focused atmosphere. We are looking for a Senior FPGA Design Engineer with outstanding technical and leadership skills. The ... & Skills + Experience with Digital Design and Architecture + RTL coding, synthesis, timing closure and lab validation + Experience with Static Timing Analysis of… more
- SpaceX (Sunnyvale, CA)
- …of coding through LINT and clock domain crossing flows + Deploy and enhance methodology and flows related to timing constraint generation and verification and ... as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base… more
- Cadence Design Systems, Inc. (Austin, TX)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... in one or more of the following areas: Synthesis, Place and Route, timing and power signoff. + Understanding and proliferating Cadence flow solutions in the… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- NVIDIA (Santa Clara, CA)
- …knowledgeable in DFT, digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... Lead. + Experience of succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is widely considered to be the leader of AI… more
- Jacobs (Dearborn, MI)
- …international motor sports community. _Jacobs is in search of a Battery Test Engineer with vehicle battery experience,_ especially high voltage. The test lab in ... OUTLINE OF SPECIFIC ROLES AND RESPONSIBILITIES Description: Battery Lab Test Engineer is responsible for supporting the Design Verification (DV) physical testing,… more
- Micron Technology, Inc. (Boise, ID)
- …world to learn, communicate and advance faster than ever. **Job Description** The Senior /Principal CAD Engineer - Parasitic Extraction is a technical role within ... and post layout netlisting and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI,… more