- Efficient Computer (San Francisco, CA)
- If you are an ASIC Physical Design Engineer who wants to impact the transformation of the next evolution of computing, we would like to talk to you. ... Efficient is hiring a senior ASIC Physical Design Engineer with experience in backend implementation from Netlist to GDSII. We seek individuals to… more
- Blue Origin (San Francisco, CA)
- …Engineering, Computer Engineering, or related technical discipline Experience with FPGA and/or ASIC design Proficiency in HDL programming (VHDL, Verilog, and/or ... Strong object‑oriented programming and scripting skills (Python, TCL, Perl) Experience with physical design flows and industry‑standard EDA tools Experience with… more
- SQL Pager LLC (San Francisco, CA)
- Principal/Senior Staff/Staff ASIC Design Engineer (RISC-V) Client Overview Client is building the first latency optimized SoC for their industry. Using its ... Job Responsibilities . We are seeking a dedicated CPU design engineer as part of ASIC...SoC level integration and verifications. . Work with the Physical design team for the timing closure… more
- OpenAI (San Francisco, CA)
- Join to apply for the Physical Design Engineer role at OpenAI About The Team OpenAI's Hardware team designs the custom silicon that powers the world's most ... Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor...area trade‑offs, working in collaboration with EDA vendors and ASIC partners Qualifications BS w/ 4+ or MS with… more
- OpenAI (San Francisco, CA)
- …a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our ... physical design team and is central to... physical design team and is central to delivering power, performance,...area trade‑offs, working in collaboration with EDA vendors and ASIC partners Qualifications: BS w/ 4+ or MS with… more
- SQL Pager LLC (San Francisco, CA)
- Principal/Senior Staff/Staff GPGPU Design Engineer Client Overview Client is building the first latency optimized SoC for their industry. Using its proven AI ... Responsibilities . We are seeking a dedicated hands-on GPGPU Design Engineer to help develop an GPGPU...SoC level integration and verifications. . Work with the Physical design team for the timing closure… more
- Career Mentors, LLC (San Francisco, CA)
- …rigor, and realism Seniority & Experience 4-10 years of experience as a Hardware Design Engineer with front-end ASIC /SoC RTL focus Proven experience in ... Founding Hardware Design Engineer (Path to Director of...constraint-heavy domains , enabling AI models to reason about, design , and validate physical systems. Starting with… more
- Renesas Electronics Corporation (San Francisco, CA)
- …static timing analysis, logic equivalent checking to post-layout checking. Experience in DFT or physical design is a plus. Experience in FPGA prototype and lab ... Application/GUI team in FPGA prototype and lab debugging. Perform physical silicon device evaluation where necessary. Qualifications 10+ years...a plus. Fluent in either Verilog RTL coding and ASIC design methodology. Competence in developing … more
- Grafton Sciences (San Francisco, CA)
- …at Grafton Sciences. About Grafton Sciences We're building AI systems with general physical ability - the capacity to experiment, engineer , or manufacture ... Senior Toolchain Engineer , Firmware Join to apply for the Senior...reproducible. This role is ideal for someone who can design production‑grade RTL and verification, understands FPGA/ ASIC … more
- Cisco Systems (San Francisco, CA)
- …and sustain strong relationships with cross-functional teams while collaborating on ASIC Design and Verification for reliable, high-performance products. Drive ... Open-minded, driven, diverse and deeply creative people at Cisco design the hardware that makes the internet work. Bring...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- Cisco (San Francisco, CA)
- … and verification, digital signal processing, memory and custom library development, physical design , DFT, signal integrity, and advanced packaging. Work with ... (eg, Python, Perl, TCL) for automation. + Familiarity with ASIC /SoC design flow including synthesis, place &... verification methodologies (eg, UVM, SystemVerilog) + Understanding of physical design and DFT ( Design … more
- Cisco (San Francisco, CA)
- …cutting-edge ASICs to production and we are looking for an experienced Reliability Engineer to join Quality and Reliability organization. Join an exciting team that ... to scale Cisco's Silicon Components business. **Your Impact** As a Product Reliability Engineer , you will play a critical role in ensuring our products meet the… more
- Cisco (San Francisco, CA)
- …Build and sustain strong relationships with cross-functional teams while collaborating on ASIC Design and Verification for reliable, high-performance products. + ... Open-minded, driven, diverse and deeply creative people at Cisco design the hardware that makes the internet work. Bring...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
