• Ayar Labs (San Jose, CA)
    …(PHY and controller) Experience in formal model equivalence checking tools and verification methodology Programming experience in Python Pay Range is $120K to ... Engineer - ASIC Design Verification Location: San Jose...with limited supervision and guidance. Essential Functions: Develop verification methodology and testbenches for digital and mixed-signal blocks Test… more
    Upward (08/05/25)
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  • Python Methodology Engineer

    Capgemini (San Jose, CA)
    **About the job you're considering** We are seeking a Python Methodology Engineer to develop Python scripts that automate the setup, execution, and ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Python Methodology Engineer / Post Silicon Validation_ **Location:** _CA-San… more
    Capgemini (10/11/25)
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  • Software Engineer I

    Cadence Design Systems, Inc. (San Jose, CA)
    …+ Leverage silicon verification platform and environment to create necessary post -silicon infrastructure, methodology and automation to allow tests executed ... We are now looking for a hands-on system integration engineer who wants to expand his/her scope, work with...SPI, SERDES, memory and many other interfaces. + Execute post -silicon tests to expose design issues, validate product against… more
    Cadence Design Systems, Inc. (10/08/25)
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