- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf of our ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . * Streamlining the timing signoff criterions, timing analysis...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. *… more
- Meta (Sunnyvale, CA)
- …tests in C for custom hardware 5. Help create and maintain design documentation including IP/ SoC Micro Architecture document (collaborator/owner), IP/ SoC ... with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4....practical experience 7. 6+ years of experience in digital design , hardware engineering or related experience 8.… more
- Google (Sunnyvale, CA)
- …of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis ( STA ), or Physical Design . **About the job** In this role, you'll work ... ASIC Design Manager, Machine Learning Accelerators, Google Cloud _corporate_fare_...+ 8 years of experience with IP Development or SoC Integration, from early architecture phase through tapeout. +… more
- Google (Sunnyvale, CA)
- …an emphasis on computer architecture. + 10 years of experience in physical design flow and methodologies for high-performance ASIC/ SoC projects. + Experience in ... Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_...(Caliber/IC Validator), Formal Verification (LEC), Extraction, Low Power Verification, STA closure, and ECO flows. + Familiarity with 2.5D/3D… more
- Google (Fremont, CA)
- …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/ SoC ) design , with a focus on both digital logic ... practical experience. + 10 years of experience in analog circuit design , including simulation and verification. + Experience working with relevant Electronic… more
- NVIDIA (Santa Clara, CA)
- … hardware engineering position. + Previous engineering experience in CPU/GPU/ SOC NPI bringup, with focus on driving methodologies and testplans. Familiarity ... a plus, related to timing, speed, reliability and power. + Familiarity with STA timing closure, circuit design , noise characterization, product binning methods… more