- SpaceX (Redmond, WA)
- RFIC Design Engineer ( Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... make this possible, with the ultimate goal of enabling human life on Mars. RFIC DESIGN ENGINEER ( SILICON ENGINEERING) At SpaceX we're leveraging our… more
- SpaceX (Redmond, WA)
- Sr. RFIC Layout Designer ( Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... this possible, with the ultimate goal of enabling human life on Mars. SR. RFIC LAYOUT DESIGNER ( SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- SpaceX (Redmond, WA)
- RF Silicon Software Engineer (Starlink) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. RF SILICON SOFTWARE ENGINEER (STARLINK) At SpaceX we're...and hardware that you create will be first-generation, supporting RF/ RFIC designs well into the future. + Design… more
- SpaceX (Redmond, WA)
- Sr. MMIC Design Engineer ( Silicon Engineering) Redmond, WA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... goal of enabling human life on Mars. SR. MMIC DESIGN ENGINEER ( SILICON ENGINEERING): At...to support critical milestones COMPENSATION AND BENEFITS: Pay range: RFIC Engineer /Senior: $160,000.00 - $220,000/per year Your… more
- Amazon (Redmond, WA)
- …communities around the world. Come work at Amazon! As Senior RF ATE Engineer , you will engage with an experienced cross-disciplinary staff to conceive and ... design innovative product solutions. You will work closely with...an open collaborative peer environment. You'll be responsible for RFIC high-volume production test methodology of mm-wave RFICs for… more
- Amazon (Redmond, WA)
- …logic and physical synthesis flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design and create timing constraints. ... * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to make sure the top level integration of analog blocks… more