- Capgemini (San Jose, CA)
- ** Senior FPGA Engineer - Bay Area...**About the Job You're Considering** 1. Hands-on experience with ** RTL design ** and **Vivado Flow (IP Integrator)** ... **multimeter** for testing and validation. **Your Skills and Experience** 1. Proficiency in ** RTL design ** and **Vivado Flow (IP Integrator)** . 2. Solid… more
- NVIDIA (Santa Clara, CA)
- …Santa Clara, CA. What you'll be doing: + Build FPGA prototypes by making RTL FPGA -friendly, partitioning the design and taking it through synthesis and ... prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our...timing and generate bit streams. + Bring up the design on FPGA prototyping platforms and indulge… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in ... and developing flows at all phases of the digital design and functional verification. It is further expected that...the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered. Position… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our ... and the full chip. You will participate in the design verification and bring-up of the chip and subsystems...in the lab bring-up of these blocks either in FPGA , emulation, or silicon by potentially writing test scripts,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * Knowledge of ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob...opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …stack development for configuration, control and status monitoring. + SystemVerilog for synthesizable RTL design + C and Python for modeling, scripting, and ... an impact on the world of technology. We are seeking a highly skilled Design Engineer to join our Palladium Solutions Development team, to drive the development of… more
- Google (Fremont, CA)
- …lead the bring-up process on various debugging stations, including, but not limited to, Field-Programmable Gate Array ( FPGA )-based platforms. Assist in ... Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_...You will require an in-depth understanding of Register-Transfer Level ( RTL ) design , digital verification, and all aspects… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we have ... computing. In this position, you will partner with the design and architecture teams to help make the right...+ Ensure code and functional coverage of all the RTL which you will verify. + Work with and… more
- Oracle (Santa Clara, CA)
- …communities and audiences, consisting of varied roles and responsibilities (eg, architects, senior designers, junior design staff, technicians, etc.). + Hands-on ... + FPGA implementation experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. \#LI-SM18 Disclaimer: **Certain US customer… more
- Amazon (Cupertino, CA)
- …as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/ FPGA design and verification tools - Experience with SOC bring-up and ... customers change the world. We are seeking a Hardware Design Engineer with role in the definition, design...generation ML Chips, Cards and server integration. As a senior member of our hardware team, you will have… more