- SpaceX (Irvine, CA)
- Sr. ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where ... with the ultimate goal of enabling human life on Mars. SR. ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric… more
- NVIDIA (Santa Clara, CA)
- …our team with varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + ... includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips. + Participate in developing… more
- Google (Sunnyvale, CA)
- …tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience ... trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC...that power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- Google (Mountain View, CA)
- …(ie, Python, Bash, Tcl) for workflow automation and data visualization. + Experience with physical design flow development and design closure for multiple ... and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the world's… more
- Microsoft Corporation (Mountain View, CA)
- …servers, clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic Microsoft Artificial ... on Chip (AISoC) Silicon team. As the Front End Methodology Engineer , you will be responsible for..., verification, design for testing( DFT) and physical design to ensure quality, performance and… more
- NVIDIA (Santa Clara, CA)
- …today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to ... needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What you'll be doing: + Develop Clock RTL generation and… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group > ASICS Engineering **General Summary:** We are looking for an ASIC Design Verification Engineer with strong CPU, ASIC design and ... team, you will be responsible for verifying the ASIC low power design , architecture and micro-architecture of by applying advanced low power verification… more
- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the ... products at Qualcomm. This role requires strong knowledge of physical design tools (like Cadence or Synopsys),...and cross-functional teams to achieve project goals and resolve design challenges. * Methodology Development: Participating in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- Qualcomm (Santa Clara, CA)
- …create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the ... flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and… more
- Google (San Diego, CA)
- …be your next career step. As a Physical Design Power Integrity Engineer , you will define on-die power grid methodology and provide solutions to meet ... more about benefits at Google (https://careers.google.com/benefits/) . + Define power grid design methodology . + Provide power grid solutions for different … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus… more
- Qualcomm (San Diego, CA)
- …**The ideal candidate will have/demonstrate the following:** + Experience in Physical design which includes floor-planning, placement, clock implementation, ... design , process technology, prior experience in flow and methodology development, block closure + Hands on experience with...degree in Electrical/Computer Engineering + 3+ years of direct physical design work experience + Strong background… more
- Qualcomm (San Diego, CA)
- …Package System Design Team at Qualcomm has an opening for Package/System Design Engineer . This team is responsible for road mapping, architecting, design ... hard macro block placement, padring, RDL and bump pattern/assignment + System level co- design methodology of IC, Package and PCB/Board + Concept analysis for… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... Primetime. + Working closely with R&D on tools and methodology improvements + Create and contribute technical content for...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- Qualcomm (San Diego, CA)
- …on QUALCOMMs Adreno Graphics cores in the area of Low Power implementation and methodology . The Power Implementation Engineer will work in QUALCOMMs Adreno GPU ... Analysis and Optimization, Performance Power and Area modeling and optimization, SOC Design implementation / methodology , Synthesis, Semi-custom design flow… more
- Actalent (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. About ... Description: Run Logic/ Physical Synthesis and generate optimized Gate Level Netlist...PTPX must have. + Experience with RTL Synthesis and design optimization for Power Performance Area. + Experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …with customers doing challenging designs at advanced nodes and help them with design implementation and signoff. Will serve as the technical expert on Cadence tools ... as well as a valued consultant on design and implementation issues. Will script up solutions or...required; 3-5 years of experience in Power Signoff and Physical Implementation of designs at 20nm and below, on… more
- Qualcomm (Santa Clara, CA)
- …> CPU Engineering **General Summary:** As a CAD Engineer focusing on the methodology and support of RTL design verification, you will work with architecture, ... Responsibilities + Work with chip leads to understand the design methodology and high level requirements in...* Leverages advanced knowledge of computer architecture, micro-architecture, logic design , circuits, and/or physical design … more