- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- NVIDIA (Santa Clara, CA)
- …optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and ... you'll be doing: + You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
- The Boeing Company (El Segundo, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will lead ... & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Lead,... and/or FPGA Design and Verification Engineers at Lead, Senior & Principal levels to join us as part… more
- BAE Systems (San Jose, CA)
- …on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO Career Site Equal Opportunity Employer. ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...chip designer who has strong proficiency in both + ASIC design- performing architecture design, RTL coding/simulation, timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus on...NVIDIA's designs + Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- NVIDIA (Santa Clara, CA)
- … Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working engineers to craft and ... + BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience) +...SOCs). + Relevant experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- NVIDIA (Santa Clara, CA)
- … Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working engineers to craft and ... core and IP integration level RTL design, synthesis, functional verification, and timing analysis using groundbreaking CAD tools and using the latest process… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- Amazon (Sunnyvale, CA)
- Description As a Sr. ASIC Design Engineer , you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... and design hardware accelerator IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional SOC development activities - Work with the… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. FPGA/ ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer , DDR IP (Silicon...development and integration + Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to… more
- Amazon (San Diego, CA)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing . Analyze simulation results, identify and ... & the impact of DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification including test plan development .… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing . + Good knowledge of extraction, device physics, STA methodology and… more
- The Boeing Company (El Segundo, CA)
- …with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Senior Static Timing Analysis (STA) engineer to join us as part ... support more Boeing Platforms. We seek an expert and senior level engineer that is ambitious and...on ASICs and FPGAs + Completed multiple first-pass success ASIC tape-outs + Experience using multiple static timing… more