• WiFi ASIC Design Verification…

    Qualcomm (Santa Clara, CA)
    …Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Science, Engineering, or related field and 1+ year of ASIC design , verification, validation, integration, or related...systems modelling language proficiency is a plus - WIFI Physical layer knowledge is a plus **Principal Duties &… more
    Qualcomm (09/19/24)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
    SpaceX (08/16/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design more
    NVIDIA (08/07/24)
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  • Senior ASIC Design Engineer…

    NVIDIA (Santa Clara, CA)
    …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
    NVIDIA (09/04/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...SOC clocking. The team collaborates with the front end design team to understand the clocking requirements for the… more
    NVIDIA (08/09/24)
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  • Senior ASIC Engineer, Timing

    NVIDIA (Santa Clara, CA)
    Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated Senior ASIC Engineer, Timing to join...intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,… more
    NVIDIA (09/23/24)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
    NVIDIA (08/31/24)
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  • Sr. SOC/ ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +...design and timing closure + Deep understanding of ASIC design flow, top-down and bottom-up … more
    SpaceX (08/24/24)
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  • Senior Logic Design Engineer-…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design more
    NVIDIA (08/22/24)
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  • Senior Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Design Engineer** to work in the dynamic Microsoft Artificial Intelligence ... program you will be interacting with various teams, including architecture, verification, and physical design , ensuring that the design is implemented and… more
    Microsoft Corporation (09/18/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …the opportunity to build complex GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design , CAD, Package Design , Software, DFT and ... NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design...design quality checks and reviews to present the physical design team with high-quality RTL What… more
    NVIDIA (08/09/24)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …of your career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of...skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a… more
    Silvus Technologies (08/21/24)
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  • Physical Design Engineer, Annapurna…

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,...3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from -… more
    Amazon (08/02/24)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    … Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic ... high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog… more
    NVIDIA (09/04/24)
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  • Senior Mask Layout Design Engineer

    NVIDIA (Santa Clara, CA)
    Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... team of Photonics, CMOS, Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits,… more
    NVIDIA (08/20/24)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... What you'll be doing: + Lead and implement IC physical layout for mixed-signal functions like high speed SerDes,...and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools.… more
    NVIDIA (07/19/24)
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  • Senior SoC Technical Program Manager,…

    Amazon (Sunnyvale, CA)
    …phases of Silicon development which are architecture definition, RTL design , Verification, IP design , Physical design , post silicon design and bring ... will interface with cross-functional engineering and program/product management teams to develop ASIC /SOC solutions that will go into Amazon Devices. In this role… more
    Amazon (09/17/24)
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  • Senior E/E & Semiconductor Engineer…

    Capgemini (Santa Clara, CA)
    …**Location: Santa Clara CA - Onsite role** **Job description:** We are looking for senior ASIC Synthesis and STA Engineer who will be responsible to prepare ... for timing and power requirements. You will work with Physical Design team to meet timings across...Bachelor or Master's(preferred or equivalent experience) degree in VLSI Design + Minimum 6 years of ASIC more
    Capgemini (09/24/24)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies...Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing. + Good knowledge… more
    NVIDIA (09/18/24)
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  • Sr. Technical Program Manager

    Amazon (San Diego, CA)
    …of Silicon development from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring up, test, characterization, ... ASIC /SOC leads) to create project execution plans for ASIC /SOC development considering all criteria to design ...used to drive multi-million dollar businesses and reporting to senior leadership Amazon is committed to a diverse and… more
    Amazon (07/24/24)
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